M Balasubramanian1*
C Nagarajan2
-
( Department of Electrical and Electronics Engineering, Government College of Engineering,
Tirunelveli, Tamil Nadu, India
profbaluindia@gmail.com
)
-
(Department of Electrical and Electronics Engineering, Muthayammal College of Engineering,
Rasipuram, Tamil Nadu, India)
Copyright © The Institute of Electronics and Information Engineers(IEIE)
Keywords
Voltage source inverter (VSI), Power quality (PQ), Renewable energy power sources (REPS), Point of common coupling (PCC), Phase locked loop (PLL), Distribution static compensator (DSTATCOM)
1. Introduction
Nowadays, many studies are carried out on the subject of renewable electricity generation
from the sun, wind, etc. since traditional energy-generating stations rely on fossil
fuels, which will be exhausted soon. Unbalanced linear and nonlinear loads cause distorted
load current, which affects the voltage profile of a weak grid formed by standalone
REPS [1]. A grid-connected VSI and advanced control techniques are essential for the effective
integration of REPS with a weak distribution grid [2,3]. Other PQ issues in a weak grid are harmonics, imbalance, reactive power demand,
islanding, etc. Due to these PQ problems, the voltage at PCC of VSI is distorted.
Shunt Active Filters (SAF) provide a better solution for current related PQ issues.
Among custom power devices, DSTATCOM is efficient at mitigating PQ problems like imbalance,
harmonics, and reactive power demand in the distribution network. Various conventional
and modern control techniques of DSTATCOM are referenced in the literature, such as
synchronous reference frame theory (SRFT) [4], instantaneous reactive power theory (IRPT) [5], instantaneous symmetrical component theory (ISCT) [6], Least Mean Square-based control algorithm [7], Combined least mean square-least mean fourth (LMS-LMF) based control algorithm [8], and so on.
It is essential to calculate the positive sequence, frequency, and phase angle of
PCC (supply) voltages to provide precise compensating current in a weak grid. To follow
the phase angle of PCC voltage, different PLL methods with improved filtering capabilities
were developed [9]. A conventional PLL is based on synchronous reference frame theory (SRF-PLL), which
uses a moving average filter (MAF) of specified window results slower dynamic response
[10]. Various PLL-based methods referenced in the literature are generally used to estimate
phase and frequency in a weak grid, such as dual SRF-PLL (DSRF-PLL) [11], complex coefficient filter-PLL (CCF-PLL) [12], multiple complex coefficient filter-PLL (MCCF-PLL) [13], second-order generalized integrator-PLL (SOGI-PLL) [14], and so on. Dual SOGI-PLL can also be used as a pre-filter to calculate the positive
sequence of supply voltages [15]. The SOGI of PLL was tuned using estimated frequency to determine the positive sequence
of supply voltages, which leads to codependency and makes the system unstable with
a high-speed PI controller. Recalculating the error and tuning the DSOGI pre-filter
with a fixed center frequency is also feasible [16-18].
This paper presents a control technique based on a frequency-fixed DSOGIPLL (FFDSOGI-PLL)
for DSTATCOM to compensate for a system with nonlinear load under weak grid conditions.
The FFDSOGI-PLL was designed for estimating the positive sequence of supply voltages
from which the unit templates of PCC voltages are determined. These unit templates
are used to generate compensating current using the SOGI block. A hysteresis current
controller (HCC) is used to produce gate pulses for the VSI switches. The detailed
analysis of the FFDSOGI-PLL-based DSTATCOM is shown in the following sections.
2. Proposed System
Fig. 1 shows the TPFW structure of the distribution network with a linear and nonlinear
load. The supply distortion is increased due to the flow of distorted load current
through the system impedance. The load, DSTATCOM, zig-zag transformer for neutral
current compensation, and the supply are connected at PCC. By processing voltages
and currents sensed at various places, the gating pulses for VSI are generated, and
the DSTATCOM injects compensating current at PCC to improve power quality.
Fig. 1. FFDSOGI-PLL control technique for DSTATCOM in TPFW system.
Fig. 1 also shows the FFDSOGI-based control algorithm for PQ enhancement in a TPFW system
with both unbalanced linear and nonlinear loads. The load current is unbalanced and
distorted. Since the same load current flows through the system impedance, PCC voltages
also become unbalanced and distorted. Therefore, the templates taken from PCC voltages
are not suitable for direct use as a reference for synchronization and generation
of a reference for DSTATCOM. Hence, the FFDSOGI-PLL-based control technique is used
to extract the positive sequence of PCC voltages.
Initially, the PCC voltages are converted to ${\alpha}$${\beta}$ components:
where $v_{ta},\,\,v_{tb},$ and $v_{tc}$ are the PCC voltages, and $v_{t\alpha }$ and
$v_{t\beta }$ are the ${\alpha}$${\beta}$ components of transformed voltages. The
transformed voltages can also be written as:
where h is the harmonic order. To calculate the fundamental positive sequence for
${\alpha}$${\beta}$ elements of PCC voltages $v_{t\alpha \beta }^{+}$, FFDSOGI is
tuned to a fundamental frequency of 50 Hz, which is free from negative sequence components
and all harmonics. Then, it is transformed to obtain positive sequence voltages $v_{\textit{tabcf}}^{+}$
.
Then, the unit templates are extracted using the positive sequence voltages and processed
with fundamental active components of the load current to determine the reference
currents.
3. Modelling and Analysis of FFDSOGI-PLL
SOGI is basically a frequency adaptive prefilter. The output signal of SOGI represents
the fundamental component of PCC voltages if the SOGI center frequency $\hat{\omega
}$ is tuned to grid frequency $\omega $. Fig. 2 shows SOGI's fundamental framework.
If the input of $v\left(t\right)=\sin \omega t$ is applied, the following expressions
are obtained:
After a transient decade under the locked condition in the above equations, the output
is equal to the input for Eq. (4), and the output is orthogonal to the input for Eq. (5). The amplitude of the output will be decreased if the input has a high-frequency
component (harmonics).
In the FFDSOGI-PLL, the tuning frequency is different from the SOGI’s tuning frequency.
In other studies [15,16], an FFDSOGI-PLL was applied for single-phase and 3-phase systems. Here, the nominal
frequency$\omega _{0}$ (50Hz) was chosen as the tuning frequency of the FFDSOGI-PLL
instead of $\hat{\omega }$ and substituted in Eqs. (4)-(7). From the equation above, if the grid frequency $\omega $ deviates from the nominal
frequency $\omega _{0}$,the amplitude and phase angle of the output signal differ.
For the given input of $v_{\alpha }\left(t\right)=\sin \omega t$and $v_{\beta }\left(t\right)=-\cos
\omega t$, the output of the FFDSOGI-PLL after transient decay is as follows:
and
with
Since the signals above require equal amplitude, they are modified by multiplying
$v_{FF,\alpha }^{'}\left(t\right)$ and $qv_{FF,\beta }^{'}\left(t\right)$ with $\frac{\hat{\omega
}}{\omega _{0}}$. Hence, the second harmonic ripple in $v_{d}\left(t\right)$ and $v_{q}\left(t\right)$
is reduced. If $\omega $ deviates from $\omega _{0}$, it is phase-shifted by $\delta
_{FF}$ as in Eq. (9). This phase shift is present in the SRF-PLL input signals $v_{\alpha ,\epsilon }^{+}\left(t\right)$
and $v_{\beta ,\epsilon }^{+}\left(t\right)$ even after the positive sequence has
been determined.
As a result of the phase angle $\theta _{\epsilon }$ changing,the calculated grid
voltage’s phase angle must be compared to the projected phase angle, $\theta =~ \omega
t$. Eq. (12) is modified for a small drift of $\omega $ from $\omega _{0}$ as follows:
Hence, the estimated phase angle is corrected to the actual value by:
The amplitude and phase angle correction using FFDSOGI are shown in Fig. 3. It should be noted that feeding $\omega $ into the multiplication for amplitude
modification has a different effect than using it to tune both SOGI filters. Because
of the stability, an additional low pass filter could be added to the SRF-PLL, which
reduces harmonics in the output signals.
Fig. 2. Basic structure of SOGI2.
Fig. 3. FFDSOGI-PLL with an estimation of positive sequence.
4. Determination of Symmetrical Components using FFDSOGI-PLL
It is easier to separate the positive sequence from harmonics compared to a negative
or zero sequence. However, the supply voltage has a higher harmonic content and is
unbalanced, and the magnitude of the positive sequence is larger than in other sequences.
As a result, a filter with a robust damping property is required. A low $k$ factor
is needed for good harmonic mitigation with the SOGI configuration. But the low $k$factorcauses
the PLL's dynamic response to be slower. The mechanism is more robust when the tuning
frequency is decoupled in the FFDSOGI-PLL, allowing for a high-speed PI controller.
Hence, an increased natural frequency$\omega _{n}$was selected to tune it. It is possible
to achieve better harmonic damping with a faster settling time.
4.1 Positive Sequence Calculation
The output of the FFDSOGI structure with amplitude adjustment and after the transient
component decaying up to $\omega =\hat{\omega }$ has four essential componentswith
a phase displacement of $\delta _{FF}$ and reduction in amplitude of:
This reduction in the amplitude is nullified by multiplying with its reciprocal amplitude.
The error in phase angle $\theta _{\epsilon }$ is minimized using Eqs. (14) and (15), which results in the actual phase angle $\hat{\theta }$. $v_{\alpha ,\epsilon }^{+}$
and $v_{\beta ,\epsilon }^{+}$ are transformed to SRF and inversely transformed ($v_{\alpha
}^{+}$ and $v_{\beta }^{+}$) using $\theta _{\epsilon }$ and $\hat{\theta }$, respectively,
which nullifies the phase error. Also, the DC signal is sent through a low pass filter
to improve harmonic damping. It is also possible to calculate the actual phase and
amplitude using the equation below.
4.2 Negative Sequence Calculation
The negative sequence is determined similarly to the positive sequence by calculating
the amplitude and phase-displaced signals using quadrature signals of the FFDSOGI
structure.
Similar to the positive sequence, the amplitude and phase displacement are calculated.
The amplitude is multiplied by $\frac{1}{K_{\epsilon }}$ and then transformed to SRF.
Also, its inverse transformation is calculated.
Fig. 4 shows an estimation of the positive and negative sequences using SRF.
Fig. 4. Compensation for phase and amplitude errors in synchronous reference frame.
4.3 Zero Sequence Calculation
The zero sequence signal is determined using Eq. (6) and then filtered using SOGI to separate third-order harmonics. It is tuned with
the assessed frequency of the FFDSOGI-PLL instead of tuning it to the fixed frequency
with recalculating error.
As shown in Fig. 5, there are two output signals from the SOGI structure.$v'_{0}$ and $qv'_{0}$ are
fundamental and quadrature signals of the zero sequence component, respectively. Then,
these signals are transformed to SRF with $\hat{\theta }$.
Fig. 5. Filter for zero sequence component.
5. FFDSOGI-PLL-based Control Algorithm
Fig. 1 shows the FFDSOGI-PLL-based control algorithm to enhance power quality in a TPFW
structure. To build a simple control technique for computing compensator reference
signals, the fundamental active components of load currents are determined. The controller
modeling process is divided into several phases, which are detailed below.
5.1 Determination of Positive Sequence PCC Voltages
An FFDSOGI-PLL-based filtering technique is used to extract the fundamental positive
sequence component of PCC voltages for generating a reference current and synchronization.
5.2 Determination of Active Components of Load Current
The 3-phase load currents’ active components $(m_{a},\,\,m_{b},\,\,m_{c})$ are determined
using the structure shown in Fig. 6. The result of SOGI has two quadrature components, which are processed to determine
the active components of load currents.
Similarly, the load current’s active components of other phases are calculated, and
their effective value is determined.
Fig. 6. SOGI block to determine active component of load currents.
5.3 Generation of Gating Pulses
DSTATCOM consists of VSI with a DC-link capacitor, which is able to compensate loads.
The power loss $m_{loss}$ in DSTATCOM inevitable since high-frequency switching is
involved. To calculate power loss $m_{loss}$, the DC-link voltage reference $V_{dc}^{\mathrm{*}}$
is compared with the measured DC link voltage $V_{dc}$, and a PI controller processes
the resulting error. The power loss $m_{loss}$ is described by the following equation:
where
error $e_{dc}\left(k\right)=V_{dc}^{*}\left(k\right)-V_{dc}\left(k\right)$
$K_{p}$ and $K_{I}$ are PI controller gain constants.
The fundamental current magnitude is the sum of $m_{loss}$ and $m_{avg}$, which corresponds
to the real power,
The pure sinusoidal and balanced templates of PCC voltages are extracted from distorted
PCC voltages using the FFDSOGI-PLL-based system. The peak value $V_{p}$ is determined
from the instantaneous PCC voltage templates $\left(v_{taf},\,\,v_{tbf},\,\,v_{tcf}\right)$
as follows:
The unit templates of PCC voltage$\left(u_{a},\,\,u_{b},\,\,u_{c}\right)$ are:
The fundamental reference supply currents $(i_{sa}^{*},\,\,i_{sb}^{*},\,\,i_{sc}^{*})$
are determined using $m_{f}$ and unit templates:
The reference supply currents above are compared with the 3-phase source current $(i_{sa},\,\,i_{sb},\,\,i_{sc})$
using HCC, and control signals for the VSI switches of DSTATCOM are generated.
6. Results and Discussion
The proposed FFDSOGI-PLL-based DSTATCOM network model was developed in a MATLAB/SIMULINK
environment. A 3-phase unbalanced RL load and a 3-phase diode bridge rectifier-fed
RL load (nonlinear load) were used. The system is supplied with the right compensation
currents via 3-phase 3-wire FFDSOGI-PLL-based DSTATCOM. Both the steady-state and
dynamic performance of DSTATCOM was analyzed.
6.1 Steady-state Performance Analysis
The following figures show the steady-state performance of the FFDSOGI-PLL-based DSTATCOM
network. The system and load details are given in Table 1.
Figs. 7(a)-(c) show the waveforms of a 3-phase load current$i_{Labc}$, compensator current $i_{fabc}$,
and source current $i_{Sabc}$. It shows that even though the load current is unbalanced
and nonlinear, the FFDSOGI-PLL-based DSTATCOM balances the source current by injecting
the compensator current.
Figs. 8(a) and (b), show the waveforms of PCC voltages, $V_{pcc}$ and FFDSOGI-PLL filtered PCC voltages.
It shows that the proposed method precisely extracts the positive sequence component
of PCC voltages. This can be used for generating a reference compensator current.
Fig. 9 shows the waveforms of the magnitude of fundamental active components of 3-phase
load currents $(m_{a},\,\,m_{b},\,\,m_{c})$, and Fig. 10(a) shows the waveform of the fundamental current magnitude related to the requirement
of total real power, $m_{f}$. Fig. 10(b) shows the waveform of unit templates of PCC voltages $u_{abc}$, which have unity
magnitude and a phase displacement of 120$^{\mathrm{o}}$from each other. Fig. 10(c) shows the waveform of fundamental reference supply currents $i_{Sabc}^{*}$, which
are the product of $m_{f}$ and $u_{abc}$.
Fig. 11 shows the waveform of the DC-link voltage $V_{dc}$ of VSI in the FFDSOGI-PLL-based
DSTATCOM. It shows that the DC-link voltage is maintained about its reference $V_{dc}^{\mathrm{*}}$
using the PI controller.
Fig. 12 shows the waveform of the phase "a" load current $i_{La}$ and its THD. Since the
load is unbalanced and nonlinear, the load current THD is increased about 18.78\%.
Figs. 13 and 14 show the waveforms of the phase "a" source current $i_{Sa}$ and PCC voltage $V_{PCCa}$
with their THD values. It shows that the FFDSOGI-PLL-based DSTATCOM compensates for
the imbalance and nonlinearity of the load current and maintains THD less than 5\%
according to IEEE standards.
Fig. 15 shows the waveforms of source voltage $V_{Sa}$ and source current $i_{Sa}$ of phase
"a". It shows that $V_{Sa}$ and $i_{Sa}$ are in phase and that the proposed compensation
technique improves the power factor to unity.
Table 1. System Parameters.
|
Parameters
|
Values
|
|
Grid supply
|
3-phase, 440 V(L-L), 50Hz
|
|
Ripple filter
|
$R_{f}$= 6${\Omega}$, $C_{f}$= 47${\mu}$F
|
|
Unbalanced linear load
|
$Z_{La}$= 5.5${\Omega}$+j15.7${\Omega}$
$Z_{Lb}$= 7${\Omega}$+j18.85${\Omega}$
$Z_{La}$= 8${\Omega}$+j22${\Omega}$
|
|
Nonlinear load
|
3-phase diode bridge rectifier fed RL load
$R$= 25${\Omega}$, $L$= 100mH
|
|
System impedance
|
$R_{s}$= 0.2${\Omega}$, $L_{s}$= 1mH
|
|
DC link capacitor
|
$C_{1}$= 1600${\mu}$F, $C_{2}$= 1600${\mu}$F
|
|
DC-link voltage reference
|
$V_{dc}^{\mathrm{*}}$= 1200V
|
|
Interfacing inductor
|
$L_{f}$= 10mH
|
|
DC PI controller gain values
|
$K_{P}$= 0.8, $K_{I}$= 0.4,
|
|
Hysteresis band
|
$\pm 0.1$ A
|
Fig. 7. System currents: (a) load current, $\mathbf{i}_{\mathbf{Labc}}$; (b) compensator current, $\mathbf{i}_{\mathbf{fabc}}$; (c) source current, $\mathbf{i}_{\mathbf{Sabc}}$.
Fig. 8. System voltages: (a) PCC voltages, $\mathbf{V}_{\mathbf{pcc}}$; (b) FFDSOGI-PLL filtered PCC voltages for reference current generation.
Fig. 9. Magnitude of fundamental active components of 3-phase load currents $(\mathbf{m}_{\mathbf{a}},\,\,\mathbf{m}_{\mathbf{b}},\,\,\mathbf{m}_{\mathbf{c}})$.
Fig. 10. Compensator internal state variables: (a) Fundamental current magnitude, $\mathbf{m}_{\mathbf{f}}\,;$ (b) Unit templates of PCC voltages,$\mathbf{u}_{\mathbf{abc}}\,;$ (c) Fundamental reference supply currents, $\mathbf{i}_{\mathbf{Sabc}}^{*}$.
Fig. 11. DC-link Voltage, $\mathbf{V}_{\mathbf{dc}}$.
Fig. 12. Phase "a" Load current $\mathbf{i}_{\mathbf{La}}$ and its THD.
Fig. 13. Phase "a" source current $\mathbf{i}_{\mathbf{Sa}}$ and its THD.
Fig. 14. Phase "a" PCC voltage $\mathbf{V}_{\mathbf{PCCa}}$ and its THD.
Fig. 15. Phase difference between source voltage $\mathbf{V}_{\mathbf{Sa}}$ and source current $\mathbf{i}_{\mathbf{Sa}}$ of phase "a".
6.2 Dynamic Performance Analysis
Fig. 16 shows the waveforms of various system parameters under a dynamic condition of imbalance
due to the phase "b" load of the system being disconnected from t=1.1s to 1.4s.The
phase "b" load current is zero from t=1.1s to 1.4s. The DSTATCOM adjusts its compensator
current in a way that the source currents are sinusoidal and balanced even under dynamic
conditions. Both the phase "b" fundamental active component $m_{b}$ and average component
$m_{avg}$ magnitude are reduced under this dynamic condition. The DC link voltage
$V_{dc}$ also slightly varies, but PCC voltages are not varied much due to these dynamics.
Hence, it is observed that the proposed controller works efficiently under both steady-state
and dynamic conditions.
Fig. 16. Dynamic performance of the system for the imbalance from t=1.1 s to 1.4 s.
7. Conclusion
The performance of the proposed FFDSOGI-PLL-based control technique has been illustrated
for DSTATCOM to compensate for unbalanced linear and nonlinear loads in a TPFW distribution
network with a weak grid. The proposed FFDSOGI-PLL was developed efficiently to estimate
both the symmetrical components and phase angle of supply voltages even under a polluted
grid environment. The proposed control algorithm’s performance in harmonic reduction,
PFC, and load balancing, etc., was validated through various simulations in MATLAB/SIMULINK
under both steady-state and dynamic conditions. Also, the source current THD was reduced
to 4.97\% according to the IEEE-519 standard by the effective compensation technique.
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Author
Balasubramanian M received a BE degree in electrical and electronics engineering
in 2006 and an ME degree (power systems) in 2009 from Anna University, Chennai, India.
He is currently working as an assistant professor in Government College of Engineering,
Tirunelveli, Tamilnadu, India. His area of interest includes active power filters,
power quality improvement in distribution systems, and renewable energy systems. He
is a lifetime member of ISTE and IEI, India.
Nagarajan C received a BE degree from K.S. Rangasamy College of Technology, India,
which is affiliated with Madras University, in 1997-2001 and an M. Tech. degree from
the Vellore Institute of Technology, Vellore, Tamilnadu, India, in 2004. He obtained
a PhD degree in electrical engineering from BIHER University, Chennai, India. At present,
he is a professor in the EEE department at Muthayammal College of Engineering, Rasipuram,
India. He has authored over 85 research publications in international and national
journals and conferences. He guided 10 research PhD scholars in Anna University, and
6 scholars are doing research under his guidelines. He published two patents. He has
been a member of the faculty at the Centre for Advanced Research, Muthayammal Engineering
College, Rasipuram, Tamilnadu, India, since 2005. His research interests include fuzzy
logic and neural network applications for power electronics and drives. He is a lifetime
member of IETE, ISTE, and IE (India) and also a member of IEEE.