Bogatin E., 2018, Signal and Power Integrity - Simplified, Prentice Hall, pp. 39-40, pp. 63-66

Fan J., Ye X., Kim J., Archambeault B., Orlandi A., 2010, Signal Integrity Design for High-speed Digital Circuits: Progress and Directions, IEEE Transactions on Electromagnetic Compatibility, Vol. 52, No. 2, pp. 392-400

Krishna K. S., Bhat M. S., 2010, Impedance Matching for the Reduction of Via Induced Signal Reflection in On-chip High Speed Interconnect Lines, in Proc. of IEEE international conference on Communication Control and Computing Technologies, pp. 120-125

Fan J., Hardock A., Rimolo-Donadio R., Müller S., Kwark Y. H., Schuster C., 2014, Efficient, Physics-based Via Modeling: Return Path, Impedance, and Stub Effect Control, IEEE Electromagnetic Compatibility Magazine, Vol. 3, No. 1, pp. 76-84

Thierauf S. C., 2017, High-Speed Circuit Board Signal Integrity, Artech House, pp. 199-202

Song K.-J., Kim J., Yoo J., Nah W., Lee J., Sim H., 2008, Low Power Noise Multilayer PCB with Discrete Decoupling Capacitors Inside, in Proc. of Electronics Packaging Technology Conference, pp. 1241-1246

Berghe S. V., Olyslager F., Zutter D. D., Moerloose J. D., Temmerman W., 1997, Power Plane Resonances as a Source of Delta-I Noise and the Influence of Decoupling Capacitors, in Proc. of International Symposium on Electromagnetic Compatibility, pp. 145-148

Smutzer C. M., Degerstrom M. J., Gilbert B. K., 2016, Navigating PCB Stackup Layer Assignments for Optimized SI and PI Performance in High Speed, High Power Designs, in Proc. of Workshop on Signal and Power Integrity

Su T., Hsu J., Ye C., Ye X., Grigoras A., 2013, Signaling Enabler in High-speed System Design by Using Hybrid Stackup Printed Circuit Board, in Proc. of International Microsystems, Packaging, Assembly and Circuits Technology Conference, pp. 85-88

Tanaka D., Mihara K., Kobayashi N., Hiyama Y., Kiyoshige S., Ichimura W., Yamaguchi T., Sudo T., 2015, Interposer design and measurement with various capacitors for reducing total system PDN impedance, in Proc. of International Conference on Electronics Packaging and iMAPS All Asia Conference, pp. 767-770

Moreira J., Moessinger M., Sasaki K., Nakamura T., 2012, Driver Sharing Challenges for DDR4 High-Volume Testing with ATE, in Proc. of International Test Conference, pp. 1-10

Yun T.-H., Kim M., 2019, Electrical Performance Analysis of Memory Test Printed Circuit Board, in Proc. of Conference of Korean Society for Precision Engineering