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REFERENCES

1 
Kim B., et al. , Apr. 2020, PCM: Precision-Controlled Memory System for Energy Efficient Deep Neural Network Training, in Proc. 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 1199-1204DOI
2 
Nguyen D. T., Hung N. H., Kim H., Lee H.-J., May. 2020, An Approximate Memory Architecture for Energy Saving in Deep Learning Applications, IEEE Transactions on Circuits and Systems for Video Technology, Vol. 67, No. 5, pp. 1588-1601DOI
3 
Lee C., Lee H., Feb. 2019, Effective Parallelization of a High-Order Graph Matching Algorithm for GPU Execution, IEEE Transactions on Circuits and Systems for Video Technology, Vol. 29, No. 2, pp. 560-571DOI
4 
Kim M., Chang I., Lee H., 2019, Segmented Tag Cache: A Novel Cache Organization for Reducing Dynamic Read Energy, IEEE Transactions on Computers, Vol. 68, No. 10, pp. 1546-1552DOI
5 
Jiang L., Zhang Y., Yang J., 2014, Mitigating write disturbance in super-dense phase change memories, in Proc. 2014 44th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, pp. 216-227DOI
6 
Lee H., Kim M., Kim H., Kim H., Lee H., 1 Dec. 2019, Integration and Boost of a Read-Modify-Write Module in Phase Change Memory System, IEEE Transactions on Computers, Vol. 68, No. 12, pp. 1772-1784DOI
7 
Kim S., Jung H., Shin W., Lee H., Lee H.-J., 2019, HAD-TWL: Hot Address Detection-Based Wear Leveling for phase-change memory systems with low latency, IEEE Computer Architecture Letters, Vol. 18, No. 2, pp. 107-110DOI
8 
Wang R., et al. , 2017, Decongest: Accelerating super-dense PCM under write disturbance by hot page remapping., IEEE Computer Architecture Letters, Vol. 16, No. 2, pp. 107-110DOI
9 
Lee H., Jung H., Lee H., Kim H., 2020, Bit-width Reduction in Write Counters for Wear Leveling in a Phase-change Memory System., IEIE Transactions on Smart Processing & Computing, Vol. 9, No. 5, pp. 413-419DOI
10 
Kim M., Lee J., Kim H., Lee. H., Jan 2020, An On-Demand Scrubbing Solution for Read Disturbance Error in Phase-Change Memory., in Proc. 2020 International Conference on Electronics, Information, Communication (ICEIC), pp. 110-111DOI
11 
Xu J., Swanson S., 2016, NOVA: A log-structured file system for hybrid volatile/non-volatile main memories, in Proc. 14th Usenix Conference on File and Storage Technologies, pp. 323-338URL
12 
Ou J., Shu J., Lu Y., 2016, A high performance file system for non-volatile main memory, in Proc. Eleventh European Conference on Computer Systems, No. 12, pp. 1-16DOI
13 
Dong M., Chen H., 2017, Soft updates made simple and fast on non-volatile memory, in Proc. 2017 USENIX Annual Technical Conference (USENIX ATC 17), pp. 719-731URL
14 
Liang L., et al. , 2016, A case for virtualizing persistent memory, in Proc. Seventh ACM Symposium on Cloud Computing (SOCC 2016), pp. 126-140DOI
15 
Mustafa N. U., Armejach A., Ozturk O., Cristal A., Unsal O. S., 2016, Implications of non-volatile memory as primary storage for database management systems, in Proc. 2016 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS), pp. 164-171DOI
16 
Wu C., Zhang G., Li K., 2016, Rethinking computer architectures and software systems for phase-change memory, ACM Journal on Emerging Technologies in Computing Systems (JETC), Vol. 12, No. 4, pp. 1-40DOI
17 
Tarasov V., Zadok E., Shepler S., 2016, Filebench: A flexible framework for file system benchmarking, login: The USENIX Magazine, Vol. 41, No. 1, pp. 6-12URL
18 
Bellard F., 2005, QEMU, a fast and portable dynamic translator, in Proc. USENIX Annual Technical Conference, FREENIX Track, Vol. 41, pp. 46URL
19 
LIBNVDIMM: Non Volatile DevicesURL
20 
NDCTLURL