| Title |
Study on Error Check and State Reduction of State Diagram Using Logic Programming |
| Authors |
이극(Lee, Geuk) ; 김민환(Kim, Min-Hwan) ; 황희융(Hwang, Hee-Yeung) |
| Abstract |
This paper is concerned with the techniques of error check and reduction of state diagram using logic programming. Error check program aims to check not only syntax errors but also semantic errors. And reduction program optimizes the state diagram by finding the redundant equivalence states and removing those from the set of states. The input of both program is state diagram represented as state table form. The output of error check program is error comment. The output of reduction program is equivalence reduced state table. Both programs are implemented using prolog. Prolog has very powerful pattern matching, and its automatic back-tracking capabilities facilitate easy-to-write error check and reduction programs. |