| Title |
Numerical Analysis of a SOI LDMOS with a Recessed Source for Low ON Resistance |
| Authors |
양회윤(Yang, Hoe-Yun) ; 김성룡(Kim, Seong-Ryong) ; 최연익(Choe, Yeon-Ik) |
| Keywords |
SOI ; LDMOS ; breakdown voltage ; on-resistance ; numerical analysis |
| Abstract |
An SOI(Silicon-On-Insulator) LD(Lateral Double-diffused)MOS with a recessed source structure is proposed to improve the on-resistance and the breakdown voltage. The recessed source structure can decrease the on-resistance by reducing the path of electron current, also increase the breakdown voltage by extending the effective length of gate field plate. Simulation results by TSUPREM4 and MEDICI have shown that the on-resistance of the LDMOS with a recessed source was 26% lower than conventional LDMOS. The breakdown voltage of proposed device was found to be 45V while that of conventional device was 36.5 V. At the same breakdown voltage of 36.5V, the on-resistance of the LDMOS with a recessed source was 41% lower than that of conventional structure. |