| Title |
Design of an Analog Content Addressable Memory Implemented with Floating Gate Treansistors |
| Keywords |
Addressable memory ; Analog Memory ; WTA ; Absolut differencing circut ; EEPROM |
| Abstract |
This paper proposes a new content-addressable memory implemented with an analog array which has linear writing and erasing characteristics. The size of the array in this memory is 2×2, which is a reasonable structure for checking the disturbance of the unselected cells during programming. An intermediate voltage, Vmid, is used for preventing the interference during programming. The operation for reading in the memory is executed with an absolute differencing circuit and a winner-take-all (WTA) circuit suitable for a nearest-match function of a content-addressable memory. We simulate the function of the mechanism by means of Hspice with 1.2μm double poly CMOS parameters of MOSIS fabrication process. |