| Title |
A Design of Instruction Based Wrapped Core Linking Module for Hierarchical SoC Test Access |
| Authors |
이현빈(Yi Hyun-Bean) ; 박성주(Park Sung-Ju) |
| Keywords |
경계스캔 설계 ; 테스트 ; SoC 테스트 ; 코아 테스트 IEEE 1149.1 ; P1500 |
| Abstract |
For a System-on-a-Chip(SoC) comprised of multiple IP cores, various design techniques have been proposed to provide diverse test link configurations. In this paper, we introduce a new instruction based Wrapped Core Linking Module(WCLM) that enables systematic integration of IEEE 1149.1 TAP'd cotes and P1500 wrapped cores with requiring least amount of area overhead compared with other state-of-art techniques. The design preserves compatibility with standards and scalability for hierarchical access. |