| Title |
A Study on the Hardware Implementation of A 3×3 Window Weighted Median Filter Using Bit-Level Sorting Algorithm |
| Keywords |
메디언 필터 ; 가중 메디언 필터 ; 정렬 알고리즘 Median filter ; Weighted median filter ; Sorting algorithm |
| Abstract |
In this paper, we studied on the hardware implementation of a 3×3 window weighted median filter using bit-level sorting algorithm. The weighted median filter is a generalization of the median filter that is able to preserve :,harp changes in signal and is very effective in removing impulse noise. It has been successfully applied in various areas such as digital signal and video/image processing. The weighted median filters are, for the most part, based on word-level sorting methods, which have more hardware and time complexity, However, the proposed bit-serial sorting algorithm uses weighted adder tree to overcome those disadvantages. It also offers a simple pipelined filter architecture that is highly regular with repeated modules and is very suitable for weighted median filtering. The algorithm was implemented by VHDL and graphical environment in MAX＋PlusII of ALTERA. The simulation results indicate that the proposed design method is more efficient than the traditional ones. |