| Title |
A Low Power scan Design Architecture |
| Authors |
민형복(Min, Hyoung-Bok) ; 김인수(Kim, In-Soo) |
| Keywords |
Scan Flipflop ; Low Power ; Scan Chain ; Scan Shift ; Test Mode ; Test Operation ; Shift Operation |
| Abstract |
Power dissipated during test application is substantially higher than power dissipated during functional operation which can decrease the reliability and lead to yield loss. This paper presents a new technique for power minimization during test application in full scan sequential circuits. This paper shows freezing of combinational logic parts during scan shift operation in test mode. The freezing technique leads to power to minimization. Significant power reduction in the scan techniques is achieved on ISCAS 89 benchmarks. |