| Title |
A 12-bit 1MS/s SAR ADC with Rail-to-Rail Input Range |
| Authors |
김두연(Kim, Doo-Yeoun) ; 정재진(Jung, Jae-Jin) ; 임신일(Lim, Shin-Il) ; 김석기(Kim, Su-Ki) |
| Keywords |
Successive Approximation Register (SAR) ; ADC ; Rail-to-Rail ; DNW ; Split capacitor |
| Abstract |
As CMOS technology continues to scale down, signal processing is favorably done in the digital domain, which requires Analog-to-Digital (A/D) Converter to be integrated on-chip. This paper presents a design methodology of 12-bit 1-MS/s Rail-to-Rail fully differential SAR ADC using Deep N-well Switch based on binary search algorithm. Proposed A/D Converter has the following architecture and techniques. Firstly, chip size and power consumption is reduced due to split capacitor array architecture and charge recycling method. Secondly, fully differential architecture is used to reduce noise between the digital part and converters. Finally, to reduce the mismatch effect and noise error, the circuit is designed to be available for Rail-to-Rail input range using simple Deep N-well switch. The A/D Converter fabricated in a TSMC 0.18um 1P6M CMOS technology and has a Signal-to-Noise-and-Distortion-Ratio(SNDR) of 69 dB and Free-Dynamic-Range (SFDR) of 73 dB. The occupied active area is 0.6mm^2. |