| Title |
Characteristics of Nanowire CMOS Inverter with Gate Overlap |
| Authors |
유제욱(Yoo, Jeuk) ; 김윤중(Kim, Yoonjoong) ; 임두혁(Lim, Doohyeok) ; 김상식(Kim, Sangsig) |
| DOI |
https://doi.org/10.5370/KIEE.2017.66.10.1494 |
| Keywords |
Silicon nanowire ; CMOS inverter ; Field effect transistor ; Gate overlap ; Bendable electronics |
| Abstract |
In this study, we investigate the influence of an overlap between the gate and source/drain regions of silicon nanowire (SiNW) CMOS (complementary metal-oxide-semiconductor) inverter on bendable plastic substrates and describe their electrical characteristics. The combination of n-channel silicon nanowire field-effect transistor (n-SiNWFET) and p-channel silicon nanowire field-effect transistor (p-SiNWFET) operates as an inverter logic gate. The gains with a drain voltage (V_{dd}) of 1 V are 3.07 and 1.21 for overlapped device and non-overlapped device, respectively. The superior electrical characteristics of each of the SiNW transistors including steep subthreshold slopes and the high I_{on}/I_{off} ratios are major factors that enable the excellent operation of the logic gate. |