KIEE - The Transactions of the Korean Institute of Electrical Engineers

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The Transactions of the Korean Institute of Electrical Engineers

The Transactions of the Korean Institute of Electrical Engineers

ISO Journal TitleTrans. Korean. Inst. Elect. Eng.

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Title	Lumped Parameter Modeling based Power Loop Analysis Technique of Power Circuit Board with Wide Conduction Area for WBG Semiconductors
Authors	조민신(Min-Shin Cho) ; 김래영(Rae-Young Kim)
DOI	https://doi.org/10.5370/KIEE.2021.70.1.079
Page	pp.79-88
ISSN	1975-8359
Keywords	WBG semiconductors; power loop; wide conduction area; lumped parameter modeling; analysis
Abstract	In this paper, we propose a power loop analysis method based on lumped parameter modeling of power circuit board with wide current conduction area for WBG power semiconductors. The proposed analysis method is modeled with lumped parameter so that power loops having various current paths can be analyzed, so the analysis is simple, easy to apply, and has the advantage of enabling dynamic power loop analysis. The validity of the lumped parameter model was verified through LTSPICE and Q3D simulation results.

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