| Title |
A Design of an AES-based Security Chip for IoT Applications using Verilog HDL |
| Authors |
박현근(Hyeon-Keun Park) ; 이광재(Kwangjae Lee) |
| DOI |
http://doi.org/10.5370/KIEEP.2018.67.1.009 |
| Keywords |
Security chip ; Hardware AES ; Field programmable Gate array ; Verilog HDL |
| Abstract |
In this paper, we introduce an AES-based security chip for the embedded system of Internet of Things(IoT). We used Verilog HDL to implement the AES algorithm in FPGA. The designed AES module creates 128-bit cipher by encrypting 128-bit plain text and vice versa. RTL simulations are performed to verify the AES function and the theory is compared to the results. An FPGA emulation was also performed with 40 types of test sequences using two Altera DE0-Nano-SoC boards. To evaluate the performance of security algorithms, we compared them with AES implemented by software. The processing cycle per data unit of hardware implementation is 3.9 to 7.7 times faster than software implementation. However, there is a possibility that the processing speed grow slower due to the feature of the hardware design. This can be solved by using a pipelined scheme that divides the propagation delay time or by using an ASIC design method. In addition to the AES algorithm designed in this paper, various algorithms such as IPSec can be implemented in hardware. If hardware IP design is set in advance, future IoT applications will be able to improve security strength without time difficulties. |