| Title |
Design of Parameters for High Power Static Var Compensator Used Cascade Multilevel Inverter |
| Authors |
민완기(Min, Wan-Ki) ; 최재호(Choi, Jae-Ho) |
| Keywords |
SVC ; Cascade Multilevel Inverter ; THD ; Parameter Design ; High Power Application |
| Abstract |
This paper examines the application of high voltage static var compensator(SVC) with cascade multilevel inverter which employs H-bridge inverter(HBI). This method has the primary advantage that the number of voltage levels can be increased for a given number of semiconductor devices when compared to the conventional control methods. The SVC system is modeled using the d-q transform which calculates the instantaneous reactive power. This model is used to design a controller and analyze the SVC system. From the mathematical model of the system, the design procedures of the circuit parameters L and C are presented in this thesis. To meet the specific total harmonic distortion(THD) and ripple factor of the capacitor voltage, the circuit parameters L and C are designed. Simulated and experimental results are also presented and discussed to validate the proposed schemes. |