Design and Implementation of an IREE Bytecode Interpreter onRISC-V SoCs for Efficient AI Inference

Design and Implementation of an IREE Compiler based RISC-V SoC Architecture for On-device AI Inference

Performance Evaluation of a Bandwidth-efficient Systolic Array with Adaptive Block-wise Data Reuse

A Design of Low-power, High-resolution Capacitance-to-pulse Time Converters based on OTA-C Integration

A 30V APT Buck Converter to Improve Efficiency of GaN Power Amplifiers in Base-station Applications

High Voltage Level Selection Swtich to improve 5G BS-PA power Efficiency

Communication-optimized Tensor Parallelism for Efficient Multi-GPU Training of Complex-valued CNNs

S2F-CLIP: CLIP-based Adaptive Fusion of Sequence and Similarity for Short-term Action Recognition

Design and Performance Analysis of a Cross-attention Transformer Model for Single-person 3D Keypoint Detection

Performance-improving Dimensionality Reduction with Tensor Decomposition and Integrated Positional Encoding