1. Introduction

As the size of technology shrinks, devices become more vulnerable to soft errors induced by radiation, and immunity to the space radiation environment decreases. Shrinking the size of technology means a smaller transistor size, smaller parasitic capacitance, and lower critical charge ^[1]. The lower the critical charge, the higher the charge that upsets a logic cell. In particular, collisions of cosmic rays (including alpha rays or neutrons) generate electron–hole pairs in a transistor, which are collected at the drain node of the transistor ^[2]. This ion strike at the drain of the transistor results in a single-event transient (SET) through the entire circuit. Furthermore, flip-flops or latches that suffer from SETs caused by ion strikes can cause permanent damage in a device. Therefore, the effect of a SET on devices has become a major concern for spacecraft avionics designers. Spacecraft avionics should be designed so that SETs do not cause an unrecoverable failure in a spacecraft ^[3]. Accordingly, engineers have been researching radiation-hardened flip-flops or latches that are robust to soft errors.

Typically, there are two categories of radiation-hardened-by-design (RHBD) flip-flops and latches ^[4]. One is system-level hardening through modular redundancies, and another is circuit-level protection by constructing a special topology of transistor connections inside a single cell. Triple modular redundancy (TMR) and dual modular redundancy (DMR) use a majority voting system and correct errors by duplicating more latches. Even if one latch fails, each latch is independent, so another latch works normally. In circuit-level RHBD, a dual interlocked cell (DICE) latch and a Quatro latch use more transistors than conventional storage cells for redundancy, and are tolerant to a single-event upset (SEU). Four storage nodes in DICE and Quatro latches are created by connecting the input and output of four inverters in an interleaved feedback configuration ^[1]. Recently, one of the circuit-level RHBD flip-flops based on a delay-based dual feedback latch was proposed ^[5]. This latch with delay-based dual feedback loops has a higher critical charge than conventional DFF, DICE, and Quatro latches. The higher the critical charge, the lower the charge that upsets a logic cell. Therefore, the FF proposed in ^[5] is also tolerant to SEU. In addition, a radiation-hardened SRAM cell that consists of an enhanced Quatro structure has been researched recently ^[6]. The proposed We-Quatro SRAM cell is robust to soft errors due to its enhanced interleaved feedback configuration, and it provides better read/write access stability compared to the conventional 6T SRAM and Quatro SRAM ^[6].

Nowadays, latches that are tolerant to double-node upset (DNU) are also being researched. For example, an HLDTL-based latch was designed to tolerate DNUs by using feedback loops and three-input Muller C-elements ^[7].

In this paper, Section 2 describes features and drawbacks of the RHBD flip-flops proposed recently. Section 3 explains the advantages of the proposed flip-flop and its mechanism for soft error correction. Section 4 shows the results from SET simulation, and compares the clock-to-Q (C2Q) delay and power consumption of the proposed flip-flop with other RHBD flip-flops. Section 5 concludes the paper.

2. Previous RHBD Flip-flops

This section reviews features and drawbacks of recently proposed RHBD flip-flops. The recently proposed high-performance and cost-effective flip-flop (HPCE FF) ^[8] shown in Fig. 1 uses XOR gates to detect and correct errors. This HPCE FF is tolerant to SETs, compared to the conventional DFF, but is very slow because the input data pass through the XOR gate. Moreover, it has more transistors than the conventional DFF because it has a shadow latch consisting of a storage DICE and XOR gates.

Second, a recently proposed DM–TSPC ^[9] uses a true single-phase clock (TSPC) and a dual modular system, as shown in Fig. 2. It has the same number of transistors as the flip-flop proposed in this paper, but is slower. The drawback of the DM-TSPC is that it does not perfectly tolerate single-node upsets (SNUs) on node Z. If SNUs occur on node Z, the erroneous data are propagated to the gate input of P10 and N11 by N10 as the CLK goes high. Thereafter, these erroneous data lead to wrong output values.

Fig. 1. Schematic of the HPCE FF proposed in [8].

Fig. 2. Schematic of the DM–TSPC proposed in [9].

3. Proposed Flip-flop

This section details the advantages of the TSPC-based RHBD flip-flop proposed herein and its mechanism of soft error correction. The proposed flip-flop is faster than recently proposed RHBD flip-flops and perfectly tolerates SNUs. Fig. 3 shows a schematic of the proposed flip-flop. It uses two TSPC flip-flops, as shown in Fig. 4, and a Muller C-element, as shown in Fig. 5. The part, except for the inverter, in the TSPC flip-flop is replicated and used as the module. The output of each module becomes input to the Muller C-element. According to Fig. 5(b), the output of the C-element changes only if the output of the modules is the same. Therefore, even if SNUs occur on any node of the flip-flop, the upset does not affect the output of the Muller C-element. This means that the proposed flip-flop is perfectly tolerant to the SNU.

There are three advantages to the proposed flip-flop. First, it uses a TSPC. TSPC-based flip-flops not only consume less power but also have a lower C2Q delay than conventional DFFs, which use both true and complementary clock signals. Moreover, true single-phase logic also leads to power-efficient clock tree networks, because only a single-phase clock is needed, and therefore, no clock skew problems arise ^[9]. Second, the proposed flip-flop uses dual modules that are independent of each other, providing the correct output even if one module fails. Third, unlike the TSPC flip-flop, the proposed flip-flop uses a Muller C-element instead of an inverter. Because this C-element only outputs data when two inputs are the same, an error in one input does not affect the output.

The most significant difference between the proposed flip-flop and the DM–TSPC is that node Z in the DM–TSPC is separated into Z1 and Z2 in the proposed flip-flop. The drawback of the proposed flip-flop is that it has more nodes where a SET can occur. However, because nodes Z1 and Z2 are independent of each other, erroneous data cannot be propagated to the output, even if one of them fails. Thus, the proposed flip-flop does not output erroneous data when a SET occurs on nodes Z1 or Z2, whereas the DM–TSPC outputs erroneous data for the duration of the SET pulse-width when the SET occurs on node Z. It outputs erroneous data only when a SET occurs simultaneously on nodes Z1 and Z2, whereas the DM–TSPC does it when a SET occurs on node Z. Moreover, the proposed flip-flop is faster than the DM-TSPC for two reasons. (1) The node capacitance of node Z in the DM-TSPC is greater than that of node Z1 for the proposed flip-flop, even though the structure of node Z in the DM-TSPC and node Z1 in the proposed flip-flop are similar. (2) The signal at node Z in the DM-TSPC is propagated to the gate of N11 and P10 by transistor N10, and then, the output is derived through the inverter. The output of the proposed flip-flop, however, is directly derived through the inverter from the combination of Z1 and Z2 nodes.

Comparisons through SET simulation waveforms are shown in the next section.

Fig. 3. Schematic of the proposed flip-flop.

Fig. 4.Schematic of the TSPC FF [9].

Fig. 5. (a) Schematic, (b) truth table of the Muller C-element used in the proposed flip-flop.

4. Simulation Results

This section shows the SET simulation results confirming that the proposed flip-flop perfectly tolerates SNUs. The proposed flip-flop, a conventional DFF, an HPCE FF, and the DM–TSPC are compared in this study, implemented in TSMC 65 nm technology. All SET simulations were conducted with the HSPICE tool, and the CLK frequency used in the simulations was 1 GHz.

To mimic a SET, current was deliberately supplied to a particular node, injecting the charge into the node. Accordingly, the injected charge changed the digital signal of the node as if a SET had occurred. The current source was modeled using a double exponential waveform ^[3], as shown in Eq. (1):

where $\textit{Q}$ is the total collected charge, ${\tau}$$_{r}$ is the rising time constant, and ${\tau}$$_{f}$ is the falling time constant.

The radiation sources used in this simulation were alpha and neutron. They were modeled to the current source deliberately injected into the transistors to mimic a SET ^[10]. Rising time constant ${\tau}$$_{r}$ usually has a value of 10 ps in silicon, and falling time constant ${\tau}$$_{f}$ is approximately five times larger than the rising time constant ^[10,11]. Therefore, ${\tau}$$_{r}$ was set to 10 ps, and ${\tau}$$_{f}$ was set to 50 ps in this simulation.

Current set value $\textit{I}$($\textit{t}$) was simulated under the same conditions for all flip-flops in this study. The range of the current was derived through current sweep analysis on all nodes to be simulated. The ranges of the current are tabulated in Tables 1 to 3, except for cases where the voltage was significantly greater than 1.2 V or under 0 V. Fig. 6(a) shows the waveform of the current sweep analysis from 10 ${\mu}$A to 200 ${\mu}$A (step size 10 ${\mu}$A) for changing the digital signal from High to Low on node Z1 of the proposed flip-flop. In addition to changing the digital signal, the range of the current was set to where the injected pulse-width was sufficiently long so that the error could be well propagated to output. According to Fig. 6(a), the range of the current was 110 ${\mu}$A to 150 ${\mu}$A. Fig. 6(b) shows the waveform of the current sweep analysis from -10 ${\mu}$A to -200 ${\mu}$A (step size -10 ${\mu}$A) for changing the digital signal from Low to High on node Z1. According to Fig. 6(b), the range of the current used for the SET simulation was -70 ${\mu}$A to -80 ${\mu}$A.

Fig. 6 is an example from Table 1 that demonstrates the transient waveform on node Z1 of the proposed flip-flop. Fig. 6(a) is the transient waveform that shows the range of the current to fluctuate the signal at node Z1 when the SNU occurred at 0.35 ns. Fig. 6(b) is the transient waveform that shows the range of the current to change the value at node Z1 when the SNU occurred at 1.35 ns. Likewise, Tables 1 to 3 present the range of the current that can fluctuate the signal at the internal node over time to run the SNU simulations in each flip-flop (Table 1 is the proposed flip-flop, Table 2 is the DM-TSPC, and Table 3 is the conventional FF). Current set value $\textit{I}$($\textit{t}$) used for the SET simulation complied with the following criteria: a sufficient change in the digital signal for all nodes to be simulated should be possible. Thus, it can exceed the range in some cases. Because this is a SET simulation, problems caused by excessive overvoltage and inversion need not be considered. In compliance with the criteria above, the maximum current set value was set to 140 ${\mu}$A for changing the digital signal from High to Low, and the minimum current set value was set to -120 ${\mu}$A for changing the digital signal from Low to High. Accordingly, $I_{\max rise }$ = 140 ${\mathrm{\mu}}$A, $I_{\max fall }$ = -120 ${\mathrm{\mu}}$A, ${\tau}$$_{r}$ = 10 ps, and ${\tau}$$_{f}$ = 50 ps. Fig. 7 shows the current source waveforms modeled with the values chosen for the SNU simulations. The modeled maximum current of the source was slightly smaller than the set value for changing the digital signal from High to Low, and the minimum current was slightly larger than the set value for changing the digital signal from Low to High.

Fig. 6. Waveforms of the current sweep analysis on node Z1 of the proposed flip-flop shown in Fig. 3. The voltage fluctuation at node Z1 is shown for current from (a) 10 μA to 200 μA (step size 10 μA) @ 0.35 ns, (b) 10 μA to -200 μA (step size -10 μA) @ 1.35 ns.

Fig. 7. Current source waveforms used in the SET simulations (a) for changing the digital signal from High to Low, (b) for changing the digital signal from Low to High.

4.1 SET Simulation Waveforms

This section shows the SET simulation waveforms for each flip-flop. Fig. 8 is a schematic of the conventional DFF. Figs. 9-11 show the SNU simulations of the proposed flip-flop, the conventional DFF, and the DM–TSPC, respectively. Fig. 12 depicts the DNU simulation of the proposed flip-flop, and Fig. 13 depicts the integrated SNU waveform of the DM–TSPC and the proposed flip-flop.

Figs. 9-13 display common waveforms for CLK, IN, and OUT. CLK was a 1 GHz clock signal used in all simulations in this study. IN is the data input of each flip-flop, and OUT is the output of each flip-flop over time. Moreover, each figure illustrates the node waveforms that were SET-simulated for each flip-flop. Figs. 9 and 12 show the waveforms of nodes Z1 and Z2 of the proposed flip-flop. Fig. 10 shows the waveform of node Y of the conventional DFF, and Fig. 11 illustrates the waveform of node Z of the DM–TSPC. As the SNU simulation waveforms of the DM–TSPC and the proposed flip-flop were integrated, Fig. 13 displays the waveform of node Z of the DM–TSPC and the waveform of node Z1 of the proposed flip-flop.

From Figs. 9-12, the normal operation waveforms are represented by black lines. The red lines in Fig. 9(b) are the simulation waveforms when the SNU occurred on node Z1 of the proposed flip-flop. The red lines in Fig. 10(b) are the simulation waveforms when the SNU occurred on node Y of the conventional DFF. Finally, the red lines in Fig. 11(b) are the simulation waveforms when the SNU occurred on node Z of the DM–TSPC. The red lines for each node in Figs. 9-12 indicate an abnormal waveform when an SNU or a DNU occurred at the internal nodes (e.g., Z1, Z2, Y, and Z) and indicate the final output (OUT) of the FFs.

Fig. 9 shows the normal operation waveform and the SNU simulation waveform of the proposed flip-flop. Fig. 10 shows the normal operation waveform and the SNU simulation waveform of the conventional DFF. Finally, Fig. 11 shows the normal operation waveform and the SNU simulation waveform of the DM–TSPC.

Fig. 9(b) shows that the proposed flip-flop tolerated the SNU. An SNU that occurred on node Z1 caused the failure of only one module of the flip-flop. Because the modules of the proposed flip-flop are independent, even if one module failed, another operated normally. In addition, the C-element outputs data only if the inputs are the same; therefore, an SNU cannot affect the output of the proposed flip-flop. However, Fig. 10(b) shows that if the SNU occurred on node Y of the conventional DFF, it would output erroneous data until the next clock edge. According to Figs. 9 and 10, the conventional DFF is vulnerable to a SET, but the proposed flip-flop perfectly tolerated the SNU.

Fig. 11(b) shows that the DM–TSPC did not fully tolerate the SNU. If the SNU occurs on node Z, it outputs erroneous data for the duration of the SET pulse-width. However, according to Fig. 9(b), when the SNU occurs on node Z1, which is the same node as node Z in the DM–TSPC, the proposed flip-flop perfectly tolerates the SNU. The proposed flip-flop outputs erroneous data for the duration of the SET pulse-width only if the soft error occurs simultaneously on nodes Z1 and Z2, as shown in Fig. 12. In Fig. 12, the normal operation waveforms are represented by black lines, and the simulation waveforms when the DNU occurs on nodes Z1 and Z2 are represented by red lines. Fig. 12 shows that if a soft error occurs simultaneously on nodes Z1 and Z2, it is inevitable for the proposed flip-flop to output erroneous data.

Fig. 13 shows the integrated SNU simulation waveform of the DM–TSPC and the proposed flip-flop. In Fig. 13, the normal operation waveforms of the DM–TSPC are represented by black dotted lines, and the simulation waveforms when the SNU occurred on node Z of the DM–TSPC are represented by red lines. The blue lines are the simulation waveforms when the SNU occurred on node Z1 of the proposed flip-flop, and the black lines are the normal operation waveforms of the proposed flip-flop. According to OUT in Fig. 13, the red line (the SNU simulation waveform when the SNU occurred on node Z of the DM–TSPC) and the black dotted line (the normal operation waveform of the DM–TSPC) have different digital signals, but the blue line (the SNU simulation waveform when the SNU occurred on node Z1 of the proposed flip-flop) has the same digital signal as the black line (the normal operation waveform of the proposed flip-flop). This means that the proposed flip-flop perfectly tolerated the SNU, compared to the DM–TSPC.

Fig. 8. Schematic of the conventional DFF [9].

Fig. 9. Waveforms of the propose flip-flop simulation (a) during normal operation (in black), (b) when the SNU occurs on node Z1 of the proposed flip-flop (in red).

Fig. 10. Waveforms of the conventional DFF simulation (a) during normal operation (in black), (b) when the SNU occurs on node Y of the conventional DFF (in red).

Fig. 11. Waveforms of the DM-TSPC simulation (a) during normal operation (in black), (b) when the SNU occurs on node Z of the DM-TSPC (in red).

Fig. 12. DNU simulation waveforms of the proposed flip-flop (normal operation is shown with black lines, and when the DNU occurs on Z1 and Z2 is shown with red lines).

Fig. 13. Combined SNU simulation waveforms of the DM–TSPC and proposed FF: normal operation of proposed FF (black sold lines) and of the DM-TSPC (dotted lines); SNU simulations of the proposed FF (blue lines), and of the DM-TSPC (red lines).

4.2 Delay and Power Efficiency in the Proposed Flip-flop

This section compares the C2Q delay and power consumption of each flip-flop. According to Table 4, because the proposed flip-flop uses a TSPC, its C2Q delay is only 82.3% of the conventional DFF. Moreover, as explained in Section 3, the proposed flip-flop is twice as fast as the DM–TSPC.

Fig. 14 shows the power consumption of the conventional DFF, the TSPC FF, the DM–TSPC, and the proposed flip-flop. Generally, TSPC-based flip-flops like the TSPC FF, the DM–TSPC, and the proposed flip-flop have higher peak power consumption but lower average power consumption than conventional DFFs. The peak power consumption of the proposed flip-flop is about 2.5 times higher than the conventional DFF. However, because the proposed flip-flop consumes less power during the transient than the conventional DFF, the average power consumption of the proposed flip-flop is less than the conventional DFF. This is because the proposed flip-flop uses a TSPC, so the transient time is significantly faster than the conventional DFF, which uses both true and complementary clocks. According to Fig. 14, a faster transient time increases the peak power consumption, but the average power consumption becomes smaller.

Moreover, the peak power consumption of the proposed flip-flop is lower than the DM–TSPC. Therefore, the average power consumption of the proposed flip-flop is also less than the DM–TSPC.

Fig. 14. Power consumption (a) the conventional DFF, (b) the TSPC FF, (c) the DM–TSPC, (d) the proposed.

Table 4. C2Q Delay and Average Power Consumption.

Flip-Flop	C2Q Delay [ps]	Normalized Delay	Average Power [μW]	Normalized Power
Conventional DFF [9]	37.429	1.000	5.803	1.000
TSPC FF [9]	22.572	0.603	3.521	0.607
DM–TSPC [9]	68.577	1.832	5.653	0.974
Proposed FF	30.818	0.823	5.412	0.933

5. Conclusion

This paper proposes a TSPC-based RHBD flip-flop that uses two TSPC flip-flops as modules and a Muller C-element. The proposed flip-flop is fully tolerant to SNUs, as well as faster and more power-efficient than the conventional DFF. Compared to the previous RHBD flip-flop mentioned in this paper, the proposed flip-flop is area-efficient because it uses only 22 transistors. Moreover, the C2Q delay of the proposed flip-flop is only 82.3% of the conventional DFF. The proposed flip-flop also consumes less power than the conventional DFF and other TSPC-based RHBD flip-flops considered in this paper.