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REFERENCES

1 
Moreau T., Sampson A., Ceze L., 2015, Approximate Computing: Making Mobile Systems More Efficient, IEEE Pervasive Computing, Vol. 14, No. 2, pp. 9-13DOI
2 
Chippa V. K., Chakradhar S. T., Roy K., Raghunathan A., 2013, Analysis and characterization of inherent application resilience for approximate computing, ACM/EDAC/IEEE Design Automation Conference (DAC), Vol. article 113, pp. 1-9DOI
3 
Gupta V., Mohapatra D., Raghunathan A., Roy K., 2013, Low-Power Digital Signal Processing Using Approximate Adders, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 32, No. 1, pp. 124-137DOI
4 
Wallace C. S., 1964, A Suggestion for a Fast Multiplier, IEEE Transactions on Electronic Computers, Vol. EC-13, No. 1, pp. 14-17DOI
5 
Momeni A., Han J., Montuschi P., Lombardi F., 2015, Design and Analysis of Approximate Compressors for Multiplication, IEEE Transactions on Computers, Vol. 64, No. 4, pp. 984-994DOI
6 
Akbari O., Kamal M., Afzali-Kusha A., Pedram M., 2017, Dual-Quality 4:2 Compressors for Utilizing in Dynamic Accuracy Configurable Multipliers, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 25, No. 4, pp. 1352-1361DOI
7 
Venkatachalam S., Ko S., 2017, Design of Power and Area Efficient Approximate Multipliers, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 25, No. 5, pp. 1782-1786DOI
8 
Ahmadinejad M., Moaiyeri M. H., Sabetzadeh F., 2019, Energy and area efficient imprecise compressors for approximate multiplication at nanoscale, AEU - International Journal of Electronics and Communications, Vol. 110DOI
9 
Kong T., Li S., 2021, Design and Analysis of Approximate 4-2 Compressors for High-Accuracy Multipliers, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 29, No. 10, pp. 1771-1781DOI
10 
Strollo A. G. M., Napoli E., De Caro D., Petra N., Meo G. D., 2020, Comparison and Extension of Approximate 4-2 Compressors for Low-Power Approximate Multipliers, IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 67, No. 9, pp. 3021-3034DOI
11 
Chang C.-H., Gu J., Zhang M., 2004, Ultra low-voltage low-power CMOS 4-2 and 5-2 compressors for fast arithmetic circuits, IEEE Trans. Circuits Syst. I Reg. Papers, Vol. 51, No. 10, pp. 1985-1997DOI
12 
Saha A., Pal R., Naik A. G., Pal D., 2018, Novel CMOS multi-bit counter for speed-power optimization in multiplier design, AEU - International Journal of Electronics and Communications, Vol. 95, pp. 189-198DOI
13 
Yang Z., Han J., Lombardi F., 2015, Approximate compressors for error-resilient multiplier design, IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS), pp. 183-186DOI
14 
Ha M., Lee S., 2018, Multipliers With Approximate 4-2 Compressors and Error Recovery Modules, IEEE Embedded Systems Letters, Vol. 10, No. 1, pp. 6-9DOI
15 
Lin C. -H., Lin I. -C., 2013, High accuracy approximate multiplier with error correction, IEEE International Conference on Computer Design (ICCD), pp. 33-38DOI
16 
Kim Y., 2019, An Accuracy Enhanced Error Tolerant Adder with Carry Prediction for Approximate Computing, IEIE Transactions on Smart Computing and Processing, Vol. 8, No. 4, pp. 324-330DOI
17 
Kim Y., 2019, A Novel Approximate Adder with Enhanced Low-Cost Carry Prediction for Error Tolerant Computing, IEIE Transactions on Smart Computing and Processing, Vol. 8, No. 4, pp. 506-510DOI
18 
Seo H., Yang Y. S., Kim Y., 2020, Design and Analysis of an Approximate Adder with Hybrid Error Reduction, Electronics, Vol. 9, No. 3, pp. 471:1-13DOI
19 
Seo H., Lee J., Lee Donghui, Kim B., Kim Y., 2021, Design and Analysis of a Low-Cost Approximate Adder with OR and Zero Truncation, IEIE Transactions on Smart Computing and Processing, Vol. 10, No. 4, pp. 309-314DOI
20 
Lee J., Seo H., Seok H., Kim Y., 2021, A Novel Approximate Adder Design using Error Reduced Carry Prediction and Constant Truncation, IEEE Access, Vol. 9, pp. 119939-119953DOI
21 
Seok H., Seo H., Lee J., Kim Y., 2021, COREA: Delay- and Energy-Efficient Approximate Adder Using Effective Carry Speculation, Electronics, Vol. 10, No. 18, pp. 2234: 1-12DOI
22 
Lee J., Seo H., Kim Y., Kim Y., 2020, Approximate adder design with simplified lower-part approximation, IEICE Electronics Express, Vol. 17, No. 15, pp. 20200218DOI
23 
Choi W., Shim M., Seok H., Kim Y., 2021., DCPA: approximate adder design exploiting dual carry prediction, IEICE Electronics Express, Vol. 18, No. 23, pp. 20210431DOI