| Title |
Development of a Multi-Defect Pattern Classification Model for Wafer Maps Using Deep Learning |
| Authors |
이지현(Ji-hyeon Lee) ; 조현종(Hyun-chong Cho) |
| DOI |
https://doi.org/10.5370/KIEE.2025.74.6.1115 |
| Keywords |
Deep Learning; Defect Analysis; Multi-Defect; Semiconductor; Wafer Map |
| Abstract |
In semiconductor manufacturing, defects on wafer maps often arise due to process-related issues. Recognizing and analyzing these defect patterns is crucial for the early detection of manufacturing faults, enabling proactive defect prediction and ultimately enhancing semiconductor yield rates. In real-world manufacturing, wafers commonly exhibit not only singular defects but also multiple concurrent defects, adding complexity to the analysis. Therefore, this study proposes a deep learning-based model for wafer map multi-defect pattern classification. We employ the ViT-B model for classification and utilize TrivialAugment to increase the diversity of wafer map images used in training. Additionally, two optimizers were applied to facilitate the smooth convergence of the model's loss function, allowing for a comparative performance evaluation. On the MixedWM38 dataset, which comprises 38 classes, our model enhanced with TrivialAugment and Adagrad achieved F1-scores of 0.984 for single defects, 0.987 for double defects, 0.982 for triple defects, and 0.986 for quadruple defects. |