김경범
(Kyungbeom Kim)
*iD
서민혁
(Minhyuck Seo)
*iD
김종민
(Jong-Min Kim)
*iD
신훈규
(Hoon-kyu Shin)
†iD
이남석
(Nam-Suk Lee)
†iD
-
(Dept. of Chemical Engineering, Dong-A University, Republic of Korea. E-mail : keibum@hanmail.net,
smh@sti.kr, jmkim3@dau.ac.kr)
Copyright © The Korean Institute of Electrical Engineers
Key Words
Silicon Carbide(SiC), Epitaxial Layer, Local Strain Accommodation
1. Introduction
Silicon carbide (SiC) is a representative wide-bandgap semiconductor with a wide bandgap,
high breakdown electric field, excellent thermal conductivity, and high electron saturation
velocity. Due to these characteristics, it has attracted attention as a key material
for high-voltage and high-power semiconductor devices in electric vehicles, renewable
energy conversion devices, and industrial power conversion systems [1].
Specifically, power semiconductors, such as SiC MOSFET (metal–oxide–semiconductor
field-effect transistor), Schottky barrier diodes, and positive-intrinsic-negative
diodes are highly dependent on the quality of the epitaxial layer [2,
3].
Homo-epitaxy, which grows the same SiC material on a SiC wafer, can minimize problems
arising from differences in lattice constants and thermal expansion coefficients.
However, minute residual stresses, crystal defects, step bunching, and changes in
surface roughness that occur during the growth process can affect device characteristics
[4–
6]. Therefore, as a key study determining the reliability and performance of high-voltage
power semiconductors, the structural analysis of the 4H-SiC epitaxial layer grown
on a SiC substrate was conducted using various analytical techniques, such as atomic
force microscopy (AFM), scanning electron microscopy (SEM), energy dispersive X-ray
spectroscopy (EDS), and high-resolution transmission electron microscopy (HR-TEM).
2. Experimental Details
2.1 SiC epitaxial growth
This study used 4H-SiC single-crystal wafers as substrates. To grow high-quality SiC
epitaxial layers, a chloride-based chemical vapor deposition process was employed
to grow 4H-SiC epitaxial layers with a thickness of 12 μm [7,
8]. The growth temperature was maintained in the range of 1600 ℃, and dichlorosilane
(DCS, H2SiCl2) and ethylene (C2H4) were used as precursors to supply Si and C, respectively. Hydrogen was used as the
carrier gas to form high-quality SiC single-crystal epitaxial layers.
SiC includes cubic, hexagonal, and rhombohedral forms that are classified based on
the stacking structure of tetrahedra along the [0001] direction, which corresponds
to the C-axis. Crystallographically, the cubic phase with a zinc-blende structure
is referred to as the β phase, while all others (hexagonal and rhombohedral phases)
with a wurtzite structure are referred to as the α phase [9,
10]. Furthermore, SiC polytypes can be distinguished by the stacking sequence even within
the same crystal structure. Over 200 SiC polytypes exist thermodynamically, and according
to Ramsdell’s notation, the stacking period of the SiC unit layer is indicated by
a number in the front, followed by C for cubic, H for hexagonal, and R for rhombohedral,
depending on the structure. For example, in Figure 1, if the stacking sequence is ‘ABCABC…’ with a cubic structure, it is denoted as 3C-SiC,
as shown in Figure 1(a). Stacking periods such as ‘ABCBABCBA…’ and ‘ABCACBABCACB…’ in hexagonal structures
are labeled as 4H-SiC and 6H-SiC, respectively, as shown in Figures 1(b) and 1(c)
[9]. The SiC polytype is determined by the order of the A, B, C positions in which the
SiC bilayer repeats along the C-axis [0001] direction. This stacking sequence is most
clearly observed in a cross-section of the (11-20) plane [11- 13].
Fig. 1 Crystallographic structure of SiC polytypes. SiC crystal structures viewed
from the zone axis [11-20]: (a) 3C-SiC, (b) 4H-SiC, and (c) 6H-SiC.
In particular, compared to other polytypes, 4H-SiC has a higher band gap energy. Its
band gap energy of 3.23 eV is about three times that of Si (the most widely used semiconductor
material). Furthermore, its saturated electron drift velocity of about 2.2 × 107 cm/s is about twice that of Si, its thermal conductivity of 4.9 W/cm·K is about three
times that of Si, and its breakdown field of 3 × 106 V/cm is over ten times higher [11]. These are highly advantageous characteristics for high-temperature device operation,
high breakdown voltage, high current, and low loss. This study analyzed the behavioral
characteristics of epitaxial layers with a 4H-SiC structure.
2.2 Sample measurements
The epitaxial layer grown on the SiC wafer was characterized using SEM, AFM, and EDS
attached to an HR-TEM. To confirm the SiC epitaxial layer grown on the SiC wafer,
the cross-section was observed using SEM (JEOL JSM-IT710HR). Elemental analysis of
the SiC was also performed via separate TEM-EDS. The surface and roughness of the
SiC epitaxial layer were analyzed using AFM (Oxford Cypher S), and the crystal structure
of the 4H-SiC epitaxial layer formed on the SiC wafer was observed at 200 kV using
HR-TEM (Cs-corrected STEM, JEOL JEM-2100F). Sample preparation for TEM imaging was
carried out using a focused ion beam (FIB, Helios 5 UX).
3. Results and Discussion
The cross-section of a six-inch SiC wafer with a 4H-SiC epitaxial layer is shown in
Figure 2. Typically, when an N-type dopant is introduced into a 4H-SiC substrate, it appears
light amber or yellow, and as the doping concentration increases, the color turns
closer to dark brown. Figure 2(a) depicts a cross-sectional image observed by SEM of the 4H-SiC epitaxial layer grown
on the SiC wafer. Since SiC is the second hardest (hardness 9.5) and brittle material
after diamond, the cross-sectional samples were prepared by laser sawing to maximize
quality without physical contact [14,
15]. As shown in Figure 2(a), the interface between the SiC wafer and the SiC epitaxial layer could be distinguished
by the contrast, and the interface is indicated with arrows. Furthermore, elemental
analysis of Si and C was conducted via scanning transmission electron microscopy (STEM)-EDS,
as shown in Figure 2(b). SiC was clearly confirmed.
Fig. 2 SiC epitaxial wafer, SEM cross-section, TEM cross-section, and EDS analysis
images: (a) SEM cross-sectional image of the interface between the grown epitaxial
layer and the 4H-SiC wafer and (b) TEM cross-sectional image and EDS elemental analysis
image of the interface between the epitaxial layer and the SiC wafer.
The surface image of the epitaxial layer grown on the SiC wafer is shown in Figure 3. The surface images were analyzed by AFM, with scan sizes of 15 μm, 5 μm, and 2 μm,
as shown in Figures 3(a), (b), and (c), respectively. In addition, the surface roughness is denoted by root mean square (RMS).
The RMS values were 178.899 pm for Figure 3(a) at a scan size of 15 μm, 188.563 pm for Figure 3(b) at a scan size of 5 μm, and 197.106 pm for Figure 3(c) at a scan size of 2 μm, confirming that the roughness was at the picometer (pm) scale
and thus extremely flat. The terrace-step structure of the 4H-SiC epitaxial layer
is formed by the step-flow growth mechanism, and local step bunching and variations
in terrace width influence the RMS roughness measured by AFM. Therefore, as the scan
size decreased, the influence of individual step edges and local surface undulations
was relatively more pronounced, which may have caused a slight increase in RMS; this
finding is consistent with the previously reported surface characteristics of SiC
epitaxial layers [16].
Fig. 3 AFM image showing the typical surface structure of the SiC epitaxial wafer.
The scan sizes were (a) 15 × 15 μm, (b) 5 × 5 μm, and (c) 2 × 2 μm.
As shown in Figure 4, the HR-TEM results revealed homo-epitaxial characteristics, with matched crystal
orientation and lattice spacing between the SiC wafer and the epitaxial layer. Figure 4 presents a high-angle annular dark-field (HAADF)–STEM image of the SiC wafer and
epitaxial layer fabricated using FIB. Notably, as in Figure 1(a), the 4H-SiC stacking structure of both the SiC wafer and the grown epitaxial layer
is indicated with red dots, which can be clearly observed in Figure 4(a)
[17,
18]. In this study, to confirm both the 4H-SiC homo-epitaxial structure and the behavior
of local strain accommodation at the interface between the SiC wafer and the SiC epitaxial
layer, HAADF-STEM analysis was conducted with the zone axis rotated to [11-20] and
[01-12], respectively, for detailed examination. Figure 4(a) displays the 4H-SiC structure described in Figure 1(b). The fast Fourier transform (FFT) pattern and crystal plane direction as viewed along
the [11-20] zone axis are shown in Figure 4(a). The actual analysis image shows that growth occurred in a homo-epitaxial manner
along the crystal orientation of the 4H-SiC wafer at the interface between the SiC
wafer and the epitaxial layer. Consequently, it was confirmed that the epitaxial layer
and wafer exhibited a homo-epitaxial relationship with the matched crystal structure
and spacing [6].
Figure 4(b) shows an HAADF-STEM image obtained with the zone axis rotated to the [01-12] direction;
unlike Figure 4(a), the stacking periodicity could not be seen, but the local strain accommodation of
atoms at the interface could be observed. The FFT pattern and crystal plane directions,
as viewed from the [01-12] zone axis, are shown in Figure 4(b). As denoted by the red squares and arrows, local shifts of the Si atomic columns
by approximately 0.01–0.05 nm (±3 pm) at the interface indicate the distribution of
micro-strain. This displacement was derived by measuring the HAADF-STEM images along
the zone axis [01-12] and analyzing the atomic column positions. Prior to measurement,
the initial normal 4H-SiC crystal structure and atomic arrangement were corrected
based on a reference lattice.
Fig. 4 SiC HAADF-STEM cross-section and FFT pattern images. (a), (b) HAADF-STEM image
of a 4H-SiC wafer with an epitaxial layer grown on it. Structural analysis and FFT
pattern image of the interface between the epitaxial layer and the SiC wafer according
to the zone axis [11-20], [01-12].
Such local stress relaxation mechanisms are also consistent with previous studies
that have reported that interfacial stress and lattice misfit can be relaxed during
the growth process in 4H-SiC homoepitaxy. However, since this study did not directly
compare samples of different thicknesses, the thickness dependence of the strain will
be further verified in future research [19,
20]. In other words, the slight lattice mismatch and residual stress at the interface
were diffused and absorbed through very small displacements of atomic positions, thereby
maintaining the structural stability of the entire crystal. Such strain relaxation
served as a key mechanism that suppressed the generation of new defects and enabled
the epitaxial layer to form a stable homo-epitaxial structure with the substrate.
In conclusion, the high-quality SiC homo-epitaxial structure of the epitaxial layer
confirmed in this study is expected to provide several positive effects for power
semiconductor devices. This study’s significance lies not in reconfirming the previously
reported homo-epitaxial relationship through HAADF-STEM and FFT pattern analysis but
in directly observing and analyzing the minute displacement of Si atomic columns and
local strain accommodation behavior occurring at the homo-epitaxial interface. These
results are may contribute to improved reliability and stability of power semiconductor
devices during their long-term operation by alleviating local stress.
4. Conclusion
This study confirmed that a 4H-SiC epitaxial layer with a thickness of 12 μm grown
on a SiC wafer exhibited a well-developed homo-epitaxial structure; furthermore, its
excellent crystalline quality, the same crystal structure as the substrate, and the
local stress generated during growth could be explained by strain accommodation. Strain
accommodation refers to the phenomenon in which stress concentrated at the interface
is gradually dispersed to adjacent atomic rows rather than accumulating at a specific
location. Therefore, the effective relaxation of stress through only minor shifts
in local atomic columns implies that a high-quality homo-epitaxial SiC epitaxial layer
was maintained without any increase in crystal defects. In particular, the HAADF-STEM
images and FFT pattern results demonstrated that local strain arising during the epitaxial
growth process could be relaxed while maintaining the continuity of the crystal structure.
Notably, these results yield crucial microstructural evidence for understanding the
structural stability of high-quality SiC epitaxial layers.
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저자소개
Kyung-Beom Kim received the B.A. degree in English Language and Literature from Handong
Global University in 2005. He is currently pursuing an integrated M.S. and Ph.D. degree
in Chemical Engineering at Dong-A University. He is currently serving as the CEO of
EMI, specializing in analysis automation and solar power modules.
Min-Hyuck Seo received the B.S. degree in Civil Engineering, with a minor in Mechanical
Engineering, from Chungbuk National University in 2016. He is currently pursuing an
integrated M.S. and Ph.D. degree in Chemical Engineering at Dong-A University. He
is currently a Director with the Operations Division, STI, Republic of Korea.
Dr. Jong Min Kim is a professor in the Department of Chemical Engineering at Dong-A
University (Republic of Korea). He has written over 50 research articles for electrochemistry,
sensor, biochemistry, polymer rheology, photochemistry and scanning probe microscopy.
His main interest is the application developments for the nano scale process techniques.
Hoon-Kyu Shin received his B.S., M.S., and Ph.D. degrees in Electrical Engineering
from Dong-A University, Busan, Korea, in 1993, 1995, and 1999, respectively. He currently
serves as a Professor in the Department of Physics at POSTECH, Director General of
the Max Planck POSTECH/Korea Research Initiative, and CEO and Founder of Nature Flower
Semiconductor Inc.
Nam-Suk Lee received the B.S degree in Electronic Engineering from Kunsan National
University, his M.S. degree in Physics from Kunsan National University in 1992 and
1995, respectively, and his Ph.D. degree in Electrical Engineering from Dong-A University
in 2007. He was a Research Professor at the Pohang University of Science and Technology
(POSTECH) NINT from 2011 to 2026, and is currently serving as Director of Semiconductor
Process Analysis at EYEQ Lab Inc. in the Republic of Korea.