| Title |
Development of Leakage Current Reduction Method in 3-Level Photovoltaic PCS |
| Authors |
Seongeun Han ; Jongmin Jo ; Hyunsung An ; Hanju Cha |
| DOI |
https://doi.org/10.6113/TKPE/2019.24.1.56 |
| Keywords |
Leakage current ; Photovoltaic PCS ; 3-level inverter ; Common mode voltage |
| Abstract |
In this study, a reduction method of leakage current in a three-level photovoltaic power-conditioning system (PCS) is proposed and verified by simulation and experiment. Leakage current generation is analyzed through an equivalent model of the common mode voltage considering a significant parasitic capacitance existing between the photovoltaic array and ground. A leakage current reduction method using pulse-width modulation (PWM) method is also proposed, and a 10-kW three-level photovoltaic PCS simulation and experiment is performed with a 1 μF parasitic capacitor based on 100 nF/kW. The proposed method using the PWM method is verified to reduce the leakage current by 73% compared with the conventional PWM method. |