| Title |
Analysis of a Synchronizing PLL System for Single-phase Grid-tie Inverters |
| Authors |
Quang-Vinh Tran ; Tae-Won Chun ; Hong-Hee Lee ; Heung-Geun Kim ; Eui-Cheol Nho |
| Keywords |
PLL; Product-type; Synchronization; Grid voltage |
| Abstract |
Recently, the reduction of standby power consumption is significantly issued in electronic and electrical industry for the conservation of environment. In the case of a switched mode power supply (SMPS), it is demanded high efficiency at extremely low output power conditions by consumers. However, it is very different from high efficiency techniques at full load conditions. In addition, many SMPSs are designed as a multi-output circuit for various loads because of cost down. This circuit is difficult to implement both high efficiency and good cross regulation performance, simultaneously. In this paper, secondary side post regulator (SSPR), current mode control method, and power sequence control technique are proposed to reduce standby power consumption and to improve cross regulation performance of the multi-output SMPSs which consist of single or multiple converter. The proposed methods are analyzed by their operational principles and optimal designs verified by experimental results with 110[W] and 270[W] SMPSs. |