| Title |
Output Voltage Synthesis and DC Link Voltage Balancing Method Based on Offset Voltage Considering Nonlinearity of Three-Level Inverters |
| Authors |
Young-Chan Jung ; Seung-Cheol Choi ; Yun-Jai Oh ; Young-Doo Yoon |
| DOI |
https://doi.org/10.6113/TKPE.2023.28.5.361 |
| Keywords |
3-Level TNPC Inverter; 3-Level Inverter DC Link Voltage Balancing; Neutral-Point Current; Inverter Nonlinearity; Dead Time Compensation |
| Abstract |
This paper proposed a DC link voltage balancing control and output voltage synthesis using offset voltage for three-level inverters. In the three-level inverter, upper/lower DC link voltage imbalance may occur depending on the switching state, and if the imbalance is large, the switching devices may be damaged. In the voltage command near the peak and valley of the carrier, the gating signal may not be generated due to dead time, and distortion may occur in the inverter output voltage and current. This paper proposed a method that limits the offset voltage synthesis region while considering inverter nonlinearity and achieves DC link voltage balancing control using the limited offset voltage. Through this method, the output voltage distortion was reduced, and the DC link voltage was balanced. The proposed method was verified through experiments on a three-level TNPC inverter and 3.7 kW induction motor. |