1. Introduction

The demands for high-speed wireless and wireline communication have rapidly increased for 5G communication systems. A phase locked loop (PLL) has an important role in synchronizing communication systems. The noise performance of a PLL is one of the major specifications that decide the bit-error rate of a system. The noise in a PLL can be categorized as deterministic and random noise.

Random noise comes from devices such as MOSFETs and resistors, which cause random jitter (RJ) that cannot be avoided ^[1]. Therefore, the RJ should be minimized by the PLL structure or advanced design techniques. Deterministic jitter (DJ) has specific frequency tones. The DJ related to the supply voltage can be suppressed by using a voltage regulator. However, the DJ caused by the reference clock signal cannot be easily filtered by the PLL structure.

Fig. 1(a) shows the power spectrum density of the output clock from a conventional PLL. There is a peak at the target frequency, and additional peaks appear because of the reference clock. The PLL architecture mixes the reference clock frequency with the output clock frequency, and unwanted reference spurs are observed at the output of the PLL.

In a classic charge-pump based PLL (CPPLL) ^[2], the phase error information is updated through a phase-frequency detector (PFD), charge pump (CP), and loop-filter (LF) in every reference clock cycle, and the control voltage of the voltage-controlled oscillator (VCO) is updated accordingly. As a result, reference spurs are unavoidable. The reference spur is mixed with various interference, which results in degradation of the overall system performance ^[3].

Design techniques have been introduced to minimize the effect of reference spur. One method is to adopt a higher order LF ^[4,5], however, the complex loop-characteristic with additional poles may cause the closed loop to be unstable. Another approach is to use a smaller loop bandwidth to provide higher attenuation of the spurs ^[6], however, the settling time increases, which is not acceptable in many applications. Furthermore, this method requires a very large area for the LF. To reduce the area, the CP current must be reduced. However, this approach degrades the signal-to-noise ratio (SNR).

In another method, the reference spur can be moved by adopting a frequency doubler ^[7]. The difference between the output clock frequency and the reference clock frequency is doubled with an edge interpolator based on a delay-locked loop (DLL). Therefore, the reference spur is reduced by the loop bandwidth of the PLL. However, due to the additional DLL-based spur-reduction architecture, larger area and power consumption cannot be avoided.

As an alternative method, a design technique has been proposed to reduce the peak of reference spur by using a pseudorandom number generator (PRNG) ^[8,9]. However, the output bits are not true random bits, so there is a limitation in that the reference spur cannot be fully spread. In this paper, a PLL with a true random number generator (TRNG) is proposed to fully spread the reference spur, as shown in Fig. 1(b). This method can reduce the reference spur while widening the loop bandwidth. The proposed architecture achieves meaningful spur spread with the TRNG.

Fig. 1. Power spectral density of PLL output (a) Conventional CPPLL, (b) Proposed TRNG-PLL.

2. Circuit Implementation

2.1 Proposed PLL with TRNG

Fig. 2 shows a conceptual timing diagram of the spur generation in PLL. As shown in Fig. 2(a), the control voltage of the VCO, $\textit{V}$$_{ctrl}$, is updated in every reference clock cycle. As a result, the reference spur is occurs. The magnitude of the reference spur at $\textit{f}$$_{target}$ ${\pm}$ $\textit{f}$$_{ref}$ can be calculated as:

(1)

$ P_{ref}=20\log (\frac{K_{VCO}\cdot \Delta V}{2\omega _{ref}})$,

where $\textit{K}$$_{VCO}$ and ${\omega}$$_{ref}$ are the gain of the VCO and frequency in radians of the reference clock, respectively. Modifying ${\omega}$$_{ref}$ to the time component, the corresponding term in (1) is:

(2)

$P_{ref}=20\log (\frac{K_{VCO}\cdot \Delta V}{4\pi }\cdot T_{ref})$,

where $\textit{T}$$_{ref}$ is the period of UP/DOWN signals. In the proposed TRNG-PLL, $\textit{T}$$_{ref}$ is randomly changed by the TRNG, as shown in Fig. 2(b), so the magnitude of the reference spur is spread within the random UP/DOWN signals delay range.

The -overall architecture of the proposed TRNG-PLL is shown in Fig. 3. Based on the CPPLL, UP/DOWN signals that contain the phase error information are delayed by the delay line. The delay line was carefully designed to maintain the pulse width of UP/DOWN signals. A voltage-controlled delay line (VCDL) is not suitable in this design because the delay coverage is half of the reference clock cycle.

If a 100MHz reference clock is used, the VCDL must change the delay as much as 5us over the PVT variations. The controllable delay with an inverter and capacitor is 50ps, which requires 10,000 delay cells and would be an ineffective design. Furthermore, the pulse widths with phase information cannot be maintained with PVT variations. Therefore, a two-step delay line with a -digitally controlled delay line (DCDL) and phase interpolator (PI) was used.

With PVT variations, the maximum delay is designed to be half of the reference clock cycle, so a NAND-based structure DCDL with a large delay control range was used ^[10]. 4-bit binary code was used to control the DCDL, which can control 16 cases of delay, as shown in Fig. 4(a). To improve the resolution of the delay, a digitally controlled PI was added. The schematic of the PI is shown in Fig. 5. The PI has 16 cases of delay with 4 binary control bits, as shown in Fig. 4(b). Therefore, the overall delay through the DCDL and PI is controlled by 8 bits from the TRNG, and 256 cases of delay can be controlled. As mentioned, the maximum delay of the DCDL and PI is limited to half of the cycle of the reference clock because the other half of the cycle is used to update the control code that delays UP/DOWN signals.

Fig. 2. Conceptual timing diagram of reference spur generation.

Fig. 3. Top block diagram of proposed TRNG-PLL.

Fig. 4. Amount of delay in delay lines verse to binary control code (a) Coarse delay tuned by DCDL, (b) Fine delay tuned by PI.

Fig. 5. The schematic of the PI.

2.2 Proposed TRNG with Digital Code Output

Generally, randomness of a random number generator (RNG) is required for data encryption to ensure information security. RNGs can be categorized as PRNG and TRNG ^[11]. The PRNG generates a random number based on a certain algorithm. Even though a PRNG has good statistically random characteristics, it has a deterministic frequency distribution that is caused by the algorithm. However, a TRNG generates a random number based on a natural noise source, so the power density of the output is evenly distributed over the frequency range. The types of TRNGs are determined by their sources of randomness.

Commonly used sources are thermal noise, flicker noise, supply-voltage noise, meta-stability, and time-to-oxide breakdown. Among these noise sources, the thermal noise caused by a resistor has similar characteristics to white noise although the output noise power is smaller than that of other noise sources. Because it has small output power, a TRNG based on a resistor can be affected by the offset and device noise from peripheral circuitry. Therefore, the output noise should be amplified by an amplifier. The proposed TRNG generates bits that randomly control the delay of UP and DOWN signals in the CPPLL.

Fig. 6 shows a top block diagram of the proposed TRNG. The noise generator (NG) was designed using resistors to generate noise signals that are amplified by an amplifier. The output data from the NG keeps changing, so a track-and-hold (T&H) circuit that operates with SAMCLK was added, and a comparator digitalizes the data. The sampler was designed by D-flip flop and decoder, which make two 4-bits signals. The 4-bit signals are fed to DCDL and PI. In an early version of proposed design, the offset voltage in the comparator was manually controlled.

Fig. 6. Top block diagram of proposed TRNG.

3. Measurement Results

The proposed TRNG-PLL was implemented in 180-nm CMOS technology. Fig. 7 shows the chip micrograph of the proposed TRNG-PLL. The occupied areas of the TRNG and CPPLL with a sampler are 0.075 mm$^{2}$ and 0.248 mm$^{2}$, respectively. The overall power consumption is 23 mW.

Fig. 8 shows that the measured reference spur is -79 dBc at the 62.5 MHz offset frequency without the TRNG. When the TRNG is enabled, the measured reference spur was suppressed by 23 dB compared to the case when the TRNG disabled. The measured integrated RMS jitter in the range of 40 kHz to 100 MHz is reduced from 24.6-ps to 10.3-ps with the help of reference spur spreading.

Fig. 8(b) shows that the integrated RMS jitter is reduced by using the proposed technique. Although the loop bandwidth increases due to the added loop delay, jitter peaking is dispersed, and the spur reduction is improved. Thus the overall integrated RMS jitter is reduced.

In Table 1, the proposed PLL is compared with previous designs. Comparing with previous works, the proposed architecture’s occupied area is reduced by suppressing the reference spur without sacrificing the loop bandwidth. In addition, meaningful spur reduction is achieved by using the true random signal.

Fig. 7. Chip microphotograph of TRNG-PLL.

Fig. 8. Measured proposed TRNG-PLL phase noise (a) TRNG is disabled, (b) TRNG is enabled.

4. Conclusion

This paper has proposed a PLL with a TRNG to reduce the reference spur in 180-nm CMOS process. The output of the TRNG was used to spread the power of the reference spur by randomly delaying the output of the PFD. The occupied area of the TRNG-PLL is 0.323 mm$^{2}$, and the power consumption is 23 mW with a 2-GHz output clock. The proposed design could be applied to wireless or wireline communication systems that need to have small reference spur.