https://doi.org/10.5573/JSTS.2024.24.2.63

(Yu-Mi Kim);(Jun Kue Park);(Woon-San Ko);(Ki-Nam Kim);(Ga-Won Lee)

In this study, we investigated the electrical and physical characteristics of ZnO TFTs with various active layer structures after exposure to different proton energies. The proton energies were 1 and 50 MeV at a fixed fluence of 1 × 1014 p/cm2. The electrical performance of the ZnO TFTs degraded after exposure to the 50 MeV proton irradiation, whereas it showed improved characteristics after the 1 MeV proton irradiation. Additionally, the performance of 1 MeV irradiated ZnO nanorods was considerably improved compared to that of the ZnO film, and an anomalous hump phenomenon disappeared. Our analysis confirmed an increase in Vo defects in the ZnO channel layer, and that low energy incident protons play a role in enhancing the conductivity of ZnO-based thin films. This suggests that ZnO TFTs with nanostructured morphology are more sensitive to proton irradiation than the ZnO film.

https://doi.org/10.5573/JSTS.2024.24.2.69

(Ji-Sub Yoon);(Doing-In Choi);(Seungyoung Park);(In-Chul Hwang)

The performance optimization of a circuit in a short time is one of the important issues for IC testing. Traditional methods depend on domain knowledge and exhaustive search (ES) for feasible parameters. In this paper, we proposed the sub-optimal control of the integrated phase noise (IPN) characteristics of RF phase lock loop (PLL) using a Bayesian optimization. For data acquisition, we designed an autonomous measurement platform based on general purpose interface bus (GPIB) and Python. Using our algorithm, we achieved performance within around 3 dB of the optimal at the 95th percentile and reduced the search time for optimal parameters by at least 98.75% compared to the ES method.

https://doi.org/10.5573/JSTS.2024.24.2.76

(Jiho Han);(Changyong Shin)

This article presents a physical unclonable function (PUF) exploiting nonlinear behaviors of bistable rings (BRs), feed-forward path, and lightweight secure architecture. To evaluate the resistance against modeling attacks based on contemporary machine learning (ML) techniques, the proposed PUF has been implemented on a 28 nm low-cost field programmable gate array (FPGA) device. One PUF with 64-bit challenge and 32-bit response only requires 2,144 look-up tables (LUTs) of hardware resource. Much bigger and more secure PUFs can also be easily built thanks to the lightweight and scalable characteristics. Experimental data shows that the proposed extensive PUF has enhanced ML attack resistance significantly better than individual BR, feed-forward, or XOR PUFs. It is infeasible for a support vector machine (SVM) to predict responses from the proposed PUF, which makes it one of the most promising candidates for extensive PUFs. Statistical analysis also delivers 48.31% of uniqueness and 98.15% of reliability, respectively.

https://doi.org/10.5573/JSTS.2024.24.2.84

(Hee-Tak Kim);(Yun-Pyo Hong);(Seok-Hun Jeon);(Tae-Ho Hwang);(Byung-Soo Kim)

Spiking neural networks (SNNs) which mimic the human brain environment have been regarded as a key role to develop human-oriented artificial intelligence (AI). Even if SNNs have lower algorithmic accuracy than recently developed deep neural networks (DNNs), spiking convolution neural networks (SCNNs) which combine convolution operation and spiking neuron achieved comparable accuracy with DNNs. However, frequent external memory access for repetitive membrane potential updates, and low hardware throughput hinder an energy-efficient SNN acceleration. In this paper, a novel dataflow that minimizes the memory access by reusing membrane data is proposed. Next, high bandwidth network-on-chip (NoC) with row stationary dataflow as well as end-to-end pipelining architecture are implemented to achieve the high throughput SCNN processor. Finally, system on chip (SoC) architecture is designed to verify the proposed SCNN processor and fabricated under 55 nm CMOS process. SCNN processor achieved the throughput of 38.4 GMAC/s in 4.35 mm2 area, and SoC chip has been verified through MNIST and Cifar10 datasets.

https://doi.org/10.5573/JSTS.2024.24.2.96

(Tae Hyun Hwang);(Sangwan Kim);(Garam Kim);(Hyunwoo Kim);(Jang Hyun Kim)

The research investigates the electrical effect of Work Function Variation (WFV) in Tunnel Field-Effect Transistors (TFETs), with Titanium Nitride (TiN) gate as a common Metal Gate material. Employing advanced Machine Learning (ML) techniques, this study seeks to establish causal relationships among various parameters, optimize ML models, and predict exceptional scenarios. Through an in-depth analysis of diverse data, the study uncovers insights into TFET’s performance variations. The ML model was optimized using the elimination method, checking each R2 value. After discovering the relevant output parameters (e.g., turn-on voltage (Von), threshold voltage (Vth)), it was observed that WFV at particular gate regions heavily affects current variation. Furthermore, ML demonstrated the ability to predict output parameters for exceptional cases, not present in the training data, such as gates composed of the 4.4-eV grain, which exhibited a high R2 value (0.9927).

https://doi.org/10.5573/JSTS.2024.24.2.105

(Quang-Huy Do);(Tan-Binh Ngo);(Sang-Woong Yoon)

We presented a CMOS lumped-element (LE) low-pass filter (LPF) with a group delay (GD) cancellation technique that uses parallel resonators comprising negative inductance and negative capacitance circuits. An inherent positive GD from the LEs of the LPF is canceled by a negative GD from the resonator. The LPF was implemented in the Global Foundry 8SF 130-nm RF CMOS Integrated Circuit (IC) technology. The core chip size was 1135 μm ? 474 μm. The maximum passband frequency of the LPF was measured to be 1.5 GHz with a return loss of more than 10 dB, in-band loss of 0.8?2.4 dB, and out-of-band roll-off rate of 41.5 dB/GHz. The GDs at frequencies below 1 GHz were 0.31?0.33 ns and decreased to zero at 1.51 GHz. The noise figures were around 13.4?17.7 dB.

https://doi.org/10.5573/JSTS.2024.24.2.111

(Jangseok Yu);(Geonwoo Lee);(Taehui Na)

In the era of big data, Von Neumann architectures, with their separation of processor and memory, face limitations in terms of bandwidth and data movement overhead. MRAM-based in-memory computing (IMC) is a promising approach to address these issues, leveraging MRAM to perform simple logical operations directly within memory. However, implementation of n-bit full adder (FA) using pre-charge sense amplifier requires “n + 1” stages. Although carry lookahead adders can reduce the number of stages, it causes significant area overhead, which makes them unsuitable for IMC applications. Therefore, it is important to explore alternatives that can minimize the number of stages. In this paper, we propose a high-performance multi-bit FA utilizing a charge saving and sharing (CSS) circuit that acquires a carry every 4 bits and performs a sum operation every 4 bits in parallel. The CSS circuit-based FA reduces the number of stages to “n/4 + 5”, while minimizing the associated area overhead.

https://doi.org/10.5573/JSTS.2024.24.2.122

(Dongha Shim);(Deokgi Kim)

This paper investigates the resistance characteristics of thin film and contact structures in a 90-nm CMOS process under cryogenic temperature and high magnetic field environment for the first time. The temperature dependences of the test structures were measured at the ambient temperatures of 300 K, 150 K, 77 K and 4.2 K, respectively. To understand the magnetic field dependence of the test structures at the temperatures, measurements were also performed under the magnetic fields of 0 T, 2 T, 4 T and 6 T, respectively. The sheet resistances and the contact resistances are analyzed along with the magnetoresistances under the various conditions. All test structures showed a decreasing sheet resistance or contact resistance as the temperature decreases. The sheet resistance of a thin films with a lower value drops faster as the temperature decreases. The metal thin film and the metal-to-n+ contact showed the maximum resistance change of 89.5% and 35%, respectively, over the temperature range. Meanwhile, negligible magnetoresistances are observed except the metal thin film, which shows a higher magnetoresistance under a lower temperature and higher magnetic field. The maximum magnetore-sistance of the metal thin film is measured to be 10.4% for the horizontal magnetic field of 6 T at 4.2 K.

https://doi.org/10.5573/JSTS.2024.24.2.128

(Hoyong Jung);(Wonkyu Do);(Cheonwi Park);(Jaehong Ko);(Young-Chan Jang)

A pipelined successive approximation register (SAR) analog-to-digital converter (ADC) is proposed for display applications. It consists of three stages and a digital error correction logic (DCL). To reduce the power consumption and area of the proposed pipelined SAR ADC, the flash ADC (FADC) and the residue amplifier of the stages 1 and 2 are shared, and the stage 3 has an architecture of 7-bit asynchronous SAR ADC using a capacitor digital-to-analog converter (CDAC). The conversion pause function of the 7-bit asynchronous SAR ADC improves the performance of the pipelined SAR ADC by stabilizing the reference voltages through non-overlapping operation between the FADC and SAR ADC. The proposed pipelined SAR ADC is designed using a 180-nm CMOS process with a supply of 1.8V. The designed pipelined SAR ADC has a SNDR of 72.97 dB and an ENOB of 11.83 bits for an analog input signal with a frequency of 4.7 MHz at a sampling rate of 10 MHz. Its area and power consumption are 0.282 mm2 and 7.9 mW, respectively.

https://doi.org/10.5573/JSTS.2024.24.2.138

(Jaewoo Lee);(Yungjun Kim);(Yoocheol Shin);(Seongjo Park);(Daewoong Kang);(Myounggon Kang)

This letter presents an in-depth investigation of the channel profile and cell current analysis of abnormal vertical 3D NAND flash memory. By utilizing 3D (technology computer-aided design) TCAD simulation, the channel profile was designed with an oxide-nitride-oxide (O/N/O) structure, providing insights into its impact on device performance. The ID-VDS curve was measured after setting the Vth target in the program state, enabling the analysis of the cell current. Additionally, the E-field of the tunneling oxide was considered to gain a comprehensive understanding of the device behavior. Based on the analysis results, the structure most vulnerable to cell current in vertical 3D NAND flash memory has been identified.

https://doi.org/10.5573/JSTS.2024.24.2.144

(Jounghoon Lim);(Jinkee Kim);(Jong Pal Kim)

A system and application for remote and continuous monitoring of tree physiological activity using four-point electrical resistance measurements are presented. To overcome traditional visual, qualitative observations of tree health, ShigometerTM was developed that uses the electrical resistance of trees. The ShigometerTM is a portable device that allows only one-time measurement with user intervention, and has a large error due to the 2-point measurement method. To overcome the shortcomings of the ShigometerTM, the world's first remote continuous measurement tree physiological activity monitoring (TPAM) system adopting the four-point measurement method was developed and validated. The TPAM system harvests energy using sunlight, simultaneously measures ambient temperature and light intensity, and transmits wirelessly using Zigbee. The developed TPAM system was applied to Zelkova trees, and as a result, it was verified that the repeatability error was improved by 8 times and the accuracy error was improved by 5 times compared to the previous ShigometerTM method. The tree resistance measurement results during the day showed a 12% variation, which means that continuous measurement monitoring for 24 hours is necessary because measurement data at any one point in the day does not represent the tree's health status.

https://doi.org/10.5573/JSTS.2024.24.2.150

(Thi Na Le);(Min Chul Suh)

The alternation of spatial exciton distribution in solution-processing organic light-emitting diodes (s-OLEDs) was exclusively studied by utilizing diffident types of host materials. The use of an n-type host material 2,2',2''-(1,3,5-Benzinetriyl)-tris(1-phenyl-1-H-benzimidazole) (TPBi) caused the electroluminescent spectral broadening accompanied with changing color coordinates upon applied voltage increase, which was being ascribed to the shift of the exciton density profile toward the hole transport layer. The extent of recombination zone shift was quantitatively examined in this study. Initially, under low luminance conditions, excitons were dispersed throughout the center of the EML. Sequentially, a large distance of 17 nm was expected for the recombination zone to shift to the interface with hole transport layer at a high voltage of 8 V. Alternatively, employing a p-type host material or a high mobility hole transport layer to prevent the overlap of recombination zone and mixing zone from happening is the way to effectively suppress this phenomenon.

https://doi.org/10.5573/JSTS.2024.24.2.158

(Huu Lam Phan);(Thi Quynh Hoa Nguyen);(Zabdiel Brito-Brito);(Fermin Mira);(Ignacio Llamas-Garro);(Jung-Mu Kim)

We report a high frequency transmission line (TL) based on spoof surface plasmon transmission. The proposed TL is designed with different shapes of bar, inverted trapezoid and trapezoid which arrange periodicity along the TL to achieve the higher field confinement and/or higher cut-off frequency. Compared with the bar-shaped TL, the TL using inverted trapezoid shape can enhance the field confinement, while the TL using trapezoid shape can be used to achieve higher cut-off frequencies up to 40 GHz. The simulation and measurement results indicate that the proposed TLs can operate with high efficiency from low frequencies up to above 28 GHz. Owing to outstanding merits such as low-cost, compact design, ease of fabrication, and good operating characteristics, the proposed TL using SSP transmission is sought to be adequate for millimeter- wave devices.