| Title |
Spiking Convolution Processor with NoC Architecture and Membrane Data Reuse Dataflow |
| Authors |
(Hee-Tak Kim);(Yun-Pyo Hong);(Seok-Hun Jeon);(Tae-Ho Hwang);(Byung-Soo Kim) |
| DOI |
https://doi.org/10.5573/JSTS.2024.24.2.84 |
| Keywords |
Spiking neural network; network on chip; spiking convolution; accelerator; data reuse |
| Abstract |
Spiking neural networks (SNNs) which mimic the human brain environment have been regarded as a key role to develop human-oriented artificial intelligence (AI). Even if SNNs have lower algorithmic accuracy than recently developed deep neural networks (DNNs), spiking convolution neural networks (SCNNs) which combine convolution operation and spiking neuron achieved comparable accuracy with DNNs. However, frequent external memory access for repetitive membrane potential updates, and low hardware throughput hinder an energy-efficient SNN acceleration. In this paper, a novel dataflow that minimizes the memory access by reusing membrane data is proposed. Next, high bandwidth network-on-chip (NoC) with row stationary dataflow as well as end-to-end pipelining architecture are implemented to achieve the high throughput SCNN processor. Finally, system on chip (SoC) architecture is designed to verify the proposed SCNN processor and fabricated under 55 nm CMOS process. SCNN processor achieved the throughput of 38.4 GMAC/s in 4.35 mm2 area, and SoC chip has been verified through MNIST and Cifar10 datasets. |