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Title [REGULAR PAPER]Area-efficient Radix-32 FFT Processor for Hand Gesture Recognition Radar
Authors Yongchul Jung(Yongchul Jung) ; Jaechan Cho(Jaechan Cho) ; Seongjoo Lee(Seongjoo Lee) ; Yunho Jung(Yunho Jung)
DOI https://doi.org/10.5573/JSTS.2019.19.3.246
Page pp.246-253
ISSN 1598-1657
Keywords FFT ; hand gesture recognition ; MDC ; radar
Abstract We propose an area-efficient fast Fourier transform (FFT) processor for hand gesture recognition (HGR) radar and present its hardware design and implementation results. To estimate finger motion, the FFT processor should support at least 600~720-point operation for three-channel input data streams. Hence, we propose three-channel 729-point FFT processor based on the radix-32 algorithm and a multipath delay commutator (MDC) pipeline architecture, which minimizes the number of non-trivial multiplications. Moreover, the FFT processor was designed using hardware description language (HDL) and synthesized to gate-level circuits using a standard cell library for 65 nm CMOS process. The proposed architecture results in a logic gate count of 219 K with die size of 0.81mm2 and required memory of 18 KB, which can be suitable for compact HGR radar, as it has a smaller area than similar processors.