| Title |
[REGULAR PAPER] An Ultrasonic Echo-signal Based Digital Background Calibration for Pipelined SAR ADC |
| DOI |
https://doi.org/10.5573/JSTS.2019.19.6.561 |
| Keywords |
Digital background calibration; pipelined SAR ADC; gradient decent algorithm; ultrasound; FPGA implementation |
| Abstract |
This paper proposes an ultrasonic echo-signal based digital background calibration technique for a pipelined SAR ADC. The proposed ADC adaptively compensates for a code-step error between two adjacent code segments by using a gradient-decent optimization algorithm. It monitors a harmonics power of ultrasonic echo signal in an ADC output and tracks the optimal step error for the minimum harmonics power. The proposed 10-bit 11-MS/s ADC was fabricated in a 0.18-?m CMOS process. The digital calibration scheme was implemented with FPGA. In measurement, a step error was tracked by applying an ultrasonic echo signal. In a single-tone measurement with the tracked step error, the SNDR was enhanced by 13.2 dB with the resultant SNDR of 56.5 dB at Nyquist-rate input. |