| Title |
[REGULAR PAPER] An Improved LDPC ECC based on System Level Reprogramming for MLC NAND Flash |
| Authors |
Jinuk Kim;Jihun Jung;Sungju Park |
| DOI |
https://doi.org/10.5573/JSTS.2020.20.1.063 |
| Keywords |
MLC flash memory; ECC; LDPC; reprogramming; data reliability |
| Abstract |
With the ever-increasing requirement for higher performance of system and memory with a huge storage capacity, Multi-Level Cell (MLC) flash memory holds a dominant position in flash memory. However, more errors are observed in flash memory as the storage size increases. Thus, various error correction techniques (e.g., Hamming, BCH, LDPC) have been adopted to maintain the reliability of data stored in flash memory. Retention error, which occurs in data that is not accessed for a long period after stored, is the major contributor of flash memory error. The incidence of retention error is highly related to p-e (program-erase) cycle of flash memory. However, in system level, flash memory should be erased before modifying data even if ECC (Error correction code) decoding is completed. This erase operation increases the p-e cycle of flash memory, resulting in high incidence of retention error. This paper introduces a safe in-place reprogramming scheme at system level to optimally correct errors without erasing. Additionally, LDPC decoding scheme uses information about the uncorrected errors to improve the performance of the LDPC decoder. Through an experiment that simulates real NAND flash memory chips, safe reprogramming scheme at system level and proposed LDPC decoding method are explicitly demonstrated. As a result of proposed in-place reprogramming, reliable retention time of data is extended. Also, proposed LDPC decoding along with safe reprogramming scheme reduced the number of average iterations up to 33% while maintaining a robust correction ability. |