| Title |
All-directional Electrostatic-discharge Protection Circuit with High Area-efficiency |
| Authors |
(Kyoung-Il Do) ; (Byung-Seok Lee) ; (Seung-Hoo Jin) ; (Yong-Seo Koo) |
| DOI |
https://doi.org/10.5573/JSTS.2021.21.4.270 |
| Keywords |
Electrostatic discharge(ESD); high current driving capability; lateral insulated gate bipolar transistor (LIGBT); silicon controlled rectifiers (SCR); holding voltage; ESD network |
| Abstract |
This paper proposes a design for a whole-chip all-directional electrostatic-discharge (ESD) protection circuit using a resistor-capacitor (RC) lateral insulated-gate bipolar transistor (LIGBT)-based 12 V power clamp and a silicon-controlled rectifier (SCR)-based 12 V input/output (I/O) clamp. The RC LIGBT-based power clamp detects pulses through an ESD detection circuit and applies a bias to the gate. Therefore, the proposed power clamp does not have snapback curve and has a low impedance during an ESD event. In addition, the structural characteristics of the proposed I/O clamp enable it to provide discharge paths for all four ESD discharge modes (PS, PD, NS, ND), and the clamp is more area efficient than conventional ESD protection circuits composed of gate-grounded n-type metal-oxide-silicon transistors or SCRs. Moreover, because floating regions are inserted in the I/O clamp and the clamp has a high holding voltage, the clamp design is resistant to latch-up, which is a critical drawback of snapback devices. Therefore, the proposed ESD protection circuit can effectively provide highly reliable protection to internal integrated circuits. The proposed circuit was fabricated using a 0.18 μm bipolar-CMOS-DMOS process, and the electrical properties and ESD robustness of the circuit were verified through a transmission line pulse measurement method and human body model surge application tests. |