| Title |
A Low-power DRAM Controller ASIC with a 36% Reduction in Average Active Power by Increasing On-die Termination Resistance |
| Authors |
(Won-Cheol Lee) ; (Ho-Jun Kim) ; (Hong-June Park) |
| DOI |
https://doi.org/10.5573/JSTS.2023.23.2.98 |
| Keywords |
DRAM controller; ASIC; low power; termination; signal integrity |
| Abstract |
A low-power DRAM controller ASIC is proposed for point-to-point interconnects such as deep learning applications. The termination resistance of the DRAM controller is increased to 160 Ω and infinity during the write and read modes, respectively, to reduce power consumption with no transmission errors. Short-reach interconnects of 25 mm DQ/DQS lines are used to avoid signal integrity issues. The proposed DRAM controller is implemented in a 65 nm process with an active area of 1.64 mm2, 16 DQ 8 Gb configuration, and a data rate of 800 Mbps per DQ pin. The DRAM interface using the proposed controller and a commercial DDR3 DRAM chip consumes 379 mW on average; this is 64% of the power with the default termination of the JEDEC standard. Derived equations for the TX and RX current of the DRAM interface reveals that the TX current of a clock signal is minimized when the time of flight of the PCB channel is integer multiples of the half period of the clock signal with large TX and RX terminations. |