| Title |
A 64-channel High-compliance Neural Stimulator IC in Standard CMOS with Sub-1nC Charge Balancing for Seizure Suppression |
| Authors |
(Seokbeom Cheon) ; (Seungah Lee) ; (Byeongseol Kim) ; (Joonsung Bae) |
| DOI |
https://doi.org/10.5573/JSTS.2025.25.6.670 |
| Keywords |
Neural stimulator; charge balancing; seizure suppression; CMOS integrated circuits; implantable; biomedical devices |
| Abstract |
We present a 64-channel implantable neural stimulator with sub-nC charge-balanced current stimulation for seizure suppression applications. The regulated cascode current driver achieves almost full VDD compliance voltage range with 98% supply voltage utilization (4.9V from 5V) in standard 0.18 μm CMOS technology, eliminating the need for expensive high-voltage processes. A passive charge balancing scheme using a bootstrapped switch with reduced on-resistance (19.56 Ω) maintains residual charge levels below 1 nC, well within the 15 nC safe limits, enabling reliable long-term operation. The stimulation parameters, including current pulse width (1 μs-1023 μs), channel activation, stimulation frequency, and current amplitude (1 μA to 1.8 mA), are highly reconfigurable through a 10 MHz SPI interface, enabling real-time adaptive stimulation protocols. The hierarchical 8 + 3-bit DAC architecture provides superior current resolution compared to existing single DAC systems while maintaining compact area efficiency of 0.0125 mm2 per channel. In-vivo animal experiments demonstrate effective seizure suppression, achieving seizure reduction within 14 seconds after 40 seconds of 5 Hz stimulation at 50 μA amplitude, validating the therapeutic efficacy of the proposed system. The fabricated IC in 0.18 μm standard CMOS process successfully combines high channel count, optimal compliance voltage utilization, enhanced safety margins, and in-vivo validation, making it suitable for practical implantable epilepsy treatment applications. |