| Title |
A Study on DC Offset Compensator Using Double SRF-PLL for Single-Phase Grid-Connected Inverter |
| Authors |
Chang-Seok Park ; Tae-Uk Jung |
| DOI |
http://dx.doi.org/10.5207/JIEIE.2016.30.6.087 |
| Keywords |
Dc Offset Error ; Compensator ; SRF-PLL ; Single-Phase Grid-Connected Inverter |
| Abstract |
This paper proposes a dc error compensation algorithm using dq synchronous reference frame phase-locked-loop in single-phase grid-connected inverters. The dc errors are caused by the process of analog-to-digital conversion and the grid voltage during measurement. If the dc offset error is included in the phase-locked-loop system, it can cause distortion in the grid angle estimation with phase-locked-loop. Accordingly, recent study has dealt with the integral technique using the synchronous reference frame phase-locked-loop method. However, the existing algorithm has a drawback that is a slow dynamic response because monitoring the one period of the grid voltage has to be required. In this paper, a dc offset error compensation algorithm for improving the response characteristic is proposed by using the SRF phase-locked-loop. The simulation and the experimental results were presented to demonstrate the effectiveness of the proposed compensation dc offset error compensation algorithm. |