| Title |
Investigation and Optimization of Double-gate MPI 1T DRAM with Gate-induced Drain Leakage Operation |
| Authors |
하종민(Jongmin Ha) ; 이재윤(Jae Yoon Lee) ; 김명선(Myeongseon Kim) ; 조성재(Seongjae Cho) ; 최일환(Il Hwan Cho) |
| DOI |
https://doi.org/10.5573/JSTS.2019.19.2.165 |
| Keywords |
1T DRAM ; middle partial insulation ; gate-induced drain leakage (GIDL) ; TCAD |
| Abstract |
In this paper, we propose a double-gate one-transistor dynamic random-access memory (1T DRAM) with middle partial insulation (MPI) structure for low power application. Low power operation with the gate-induced drain leakage (GIDL) programming method can be obtained while maintaining the original advantages of MPI 1TDRAM. The optimization of the MPI 1T-DRAM device for the GIDL method is investigated with technology computer-aided design (TCAD). High current ratio and low power consumption are obtained from the proposed 1T-DRAM device. Optimal device design in terms of barrier insulator length and fin width have been carried out for improvements of device performances and reliability. |