Mobile QR Code QR CODE

REFERENCES

1 
Nitayama A., Kohyama Y., Hieda K., Dec. 1998, Future directions for DRAM memory cell technology, Tech. Dig. IEEE IEDM, pp. 355-358DOI
2 
Jeon D. I., Chung K. S., Jun. 2018, DRBAC: Dynamic row buffer access control for power and performance of DRAM systems, J. Semicond. Technol. Sci., Vol. 18, No. 3, pp. 307-314DOI
3 
Jung J. W., Han S. B., Lee K., Mar. 2001, W Polymetal Gate Technology for Giga Bit DRAM, J. Semicond. Technol. Sci., Vol. 1, No. 1, pp. 31-39Google Search
4 
Radens C. J., et al , Dec. 2000, An orthogonal 6F2 trench-sidewall vertical device cell for 4 Gb/16 Gb DRAM, Tech. Dig. IEEE IEDM, pp. 349-352DOI
5 
Kim S., Yang H., Dec. 2017, Dual-port SDRAM Architecture for Low-power Communication of Internet-of-things Devices, J. Semicond. Technol. Sci., Vol. 17, No. 6, pp. 893-903DOI
6 
Kuo C., King T. J., Hu C., Dec. 2002, A capacitorless double-gate DRAM cell design for high density applications, Tech. Dig. IEEE IEDM, pp. 843-846DOI
7 
Fazan P., et al , Oct. 2002, Capaitor-less 1-transistor DRAM, Proc. 2002 IEEE Int. SOI Conf., pp. 10-13Google Search
8 
Okhonin S., Nagoga M., Sallese J. M., Fazan P., Aug. 2002, A capacitor-less 1T DRAM cell, IEEE Electron Device Lett., Vol. 23, No. 2, pp. 85-87DOI
9 
Sasaki N., Nakano M., Iwai T., Togei R., Dec. 1978, Charge pumping SOS-MOS transistor memory, Tech. Dig. IEEE IEDM, pp. 356-359DOI
10 
Tack M. R., Gao M., Claeys C. L., Declerck G. J., May 1990, The multistable charge-controlled memory effect in SOI MOS transistors at low temperatures, IEEE Trans. Electron Devices, Vol. 37, No. 5, pp. 1373-1382DOI
11 
Wann H. J., Hu C., Dec. 1993, A capacitorless DRAM cell on SOI substrate, Tech. Dig. IEEE IEDM, pp. 635-638DOI
12 
Ohsawa T., et al , Jun. 2003, A memory using one-transistor gain cell on SOI (FBC) with performance suitable for embedded DRAM’s, IEEE VLSI Tech. Dig., pp. 93-96DOI
13 
Chen C. H., et al , Nov. 2010, A novel MOSFET with bMPI structure for 1T-DRAM application, 2010 IEEE International Symposium on Next Generation Electronics, pp. 133-135DOI
14 
Tian Y., Huang R., Zhang X., Wang Y., Mar. 2005, A novel nanoscaled device concept: quasi-SOI MOSFET to eliminate the potential weaknesses of UTB SOI MOSFET, IEEE Trans. Electron Devices, Vol. 52, No. 4, pp. 561-568DOI
15 
Ertosun M. G., Cho H., Kapur P., Saraswat K. C., Jun. 2008, A Nanoscale Vertical Double-Gate Single-Transistor Capacitorless DRAM, IEEE Electron Device Lett., Vol. 29, No. 6, pp. 615-617DOI
16 
Yoshida E., Tanaka T., Apr. 2006, A capacitorless 1T-DRAM technology using gate-induced drain-leakage (GIDL) current for low-power and high-speed embedded memory, IEEE Trans. Electron Devices, Vol. 53, No. 4, pp. 692-697DOI
17 
Mahmud F. A., Islam Md. M., Hasan Maruf Md., Feb. 2017, Comparative study on single-gate MOSFET and double gate MOSFET, Appl. Res. J., Vol. 3, No. 2, pp. 80-86Google Search
18 
Ha J., Lee J. Y., Kim M., Cho S., Cho I. H., Jul. 2018, Investigation and optimization of double gate MPI 1T-DRAM structure with gate induced drain leakage operation, Proc. Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices (AWAD), pp. 229-231Google Search
19 
Hou J., Shao Z., Miao X., Dec. 2009, A High speed low power capacitorless SOI-DRAM cell using impact ionization and GIDL effect, Proc. 2009 IEEE Int. Conf. Electron Devices and Solid-State Circuits (EDSSC), pp. 517-520DOI
20 
Lin J. T., Lin P. H., Eng Y. C., Chen Y. R., May 2013, Novel Vertical SOI-Based 1T-DRAM With Trench Body Structure, IEEE Trnas. Electron Devices, Vol. 60, No. 6, pp. 1872-1877DOI
21 
Fan J., et al , Dec. 2014, Insight Into Gate-Induced Drain Leakage in Silicon Nanowire Transistors, IEEE Trans. Electron Devices, Vol. 62, No. 1, pp. 213-219DOI