| Title |
[SPECIAL ISSUE] A MIPI Receiver Bridge Chip Supporting 5-Gb/s/lane D-PHY and 3-Gsymbol/s/lane C-PHY |
| Authors |
Seokwon Choi;Pil-Ho Lee;Jin-Wook Han;Sang-Dong Kim;Young-Chan Jang |
| DOI |
https://doi.org/10.5573/JSTS.2020.20.1.029 |
| Keywords |
Receiver bridge chip; MIPI; D-PHY; C-PHY; deserializer; equalizer; clock recovery |
| Abstract |
A receiver bridge chip, which supports both the D-PHY version 2.0 and the C-PHY version 1.1 specifications of the mobile industry processor interface (MIPI), is proposed to be used in a field-programmable gate array (FGPA)-based frame grabber supporting the MIPI camera industry serial interface-2. The MIPI D-PHY receiver consists of four data lanes and one clock lane. Each data lane consists of a high-speed receiver with equalizer and a 1-to-8 deserializer including a byte detector for the parallel interface with the FPGA, and supports a data rate of 5 Gb/s/lane. The MIPI C-PHY receiver consists of three lanes. Each lane includes a current mirror amplifier-based high-speed receiver, a clock recovery with deglitch circuit, a 3-to-21 deserializer, and a 21-to-16 demapper, and supports a data rate of 3 Gsymbol/s/lane. The proposed receiver bridge chip supporting the MIPI D-PHY and C-PHY is implemented as a single chip using a 0.11-μm CMOS process with 1.2-V supply. The area of the single chip is 3.15 mm × 3.15 mm. The power consumption of the MIPI D-PHY and C-PHY is 157.5 mW and 265.8 mW, respectively. |