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“JSTS has been indexed and abstracted in the SCIE (Science Citation Index Expanded) since Volume 9, Issue 1 in 2009. Furthermore, it continues to maintain its listing in the SCOPUS database and is recognized as a regular journal by the Korea Research Foundation.

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REFERENCES

1 
Balamurugan G., et al. , Apr 2008, A scalable 5–15 Gbps, 14–75 mW low-power I/O transceiver in 65 nm CMOS, IEEE J. Solid-State Circuits, Vol. 43, No. 4, pp. 1010-1019DOI
2 
Kim E. J., et al. , Aug 2010, Unified dual mode physical layer for mobile CMOS image sensor interface, IEEE Trans. Consumer Electronics, Vol. 56, No. 3, pp. 1196-1203DOI
3 
Tikka T., et al. , June 2014, A 1.2 – 6.4 GHz Clock Generator with a Low-Power DCO and Programmable Multiplier in 40-nm CMOS, IEEE Int. Symposium on Circuit and Symtems, pp. 506-509DOI
4 
MIPI Alliance , Nov 2015, MIPI Alliance Specification for D-PHY, version 2.0Google Search
5 
MIPI Alliance , Dec 2015, MIPI Alliance Specification for D-PHY, version 1.1Google Search
6 
Suzuki A., et al. , Feb 2015, A 1/1.7-inch 20Mpixel Back-Illuminated Stacked CMOS Image Sensor for New Imaging Applications, IEEE Int. Solid-State Circuits Conf., pp. 110-112DOI
7 
Lattice Semiconductor , June 2015, MIPI D-PHY Bandwidth Matrix Table User Guide, version 1.0Google Search
8 
Meticom GmbH , Aug 2016, Channel FPGA to MIPI D-PHY Bridge IC MC20902 datasheet, version 1.07Google Search
9 
Lee P.-H., et al. , Aug 2017, A 10-Gbps receiver bridge chip with deserializer for FPGA-based frame grabber supporting MIPI CSI-2, IEEE Trans. on Consumer Electronics, Vol. 63, No. 3, pp. 209-215DOI
10 
Choi S., et al. , Feb 2019, 5-Gb/s/lane D-PHY and 3-Gsymbol/s/lane C-PHY Receiver Bridge Chip, The 26th Korean Conference on Semiconductors, pp. 836Google Search
11 
Han J.-W., et al. , Nov 2017, A clock recovery for 2.56 GSymbol/s MIPI C-PHY receiver, IEEE International SoC Design Conference, pp. 246-247DOI
12 
Kaviani K., et al. , Mar 2013, A 0.4-mW/Gb/s Near-Ground Receiver Front-End With Replica Trans-conductance Termination Calibration for a 16-Gb/s Source-Series Terminated Transceiver, IEEE J. Solid-State Circuits, Vol. 48, No. 3, pp. 636-648DOI
13 
Choi W., et al. , Feb 2017, A 1V 7.8mW 15.6Gb/s C-PHY transceiver using tri-level signaling for post-LPDDR4, IEEE Int. Solid-State Circuits Conf., pp. 402-403DOI