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Title [SPECIAL ISSUE] Investigation of Line-edge Roughness Effects on Electrical Characteristics of Nanowire Tunnel FETs and MOSFETs
Authors Jang Hyun Kim;Min Gyu Lee;Seong-Su Shin;Sangwan Kim
DOI https://doi.org/10.5573/JSTS.2020.20.1.041
Page pp.41-46
ISSN 1598-1657
Keywords Tunnel field-effect transistor; TFET; line-edge roughness; LER effect; correlation coefficients
Abstract In this paper, the influences of design parameters on the line-edge roughness (LER) effects in a nanowire tunnel field-effect transistor (TFET) and a metal-oxide-semiconductor FET (MOSFET) have been discussed with the help of technology computer-aided design simulation. The strength of LER effects are quantitatively examined by correlation coefficients (R) between electrical performances and variations of nanowire dimensions; 1) threshold voltage (Vth) vs. channel volume, 2) ON-state current (ION) vs. channel volume, 3) Vth vs. source-channel junction area, and 4) ION vs. source-channel junction area. According to the simulation results, the nanowire MOSFET shows the similar values from 0.47-R to 0.74-R for all cases. On the other hand, the nanowire TFET only depends on the variation in the source-channel junction area with R more than 0.4.