Mobile QR Code QR CODE

“JSTS has been indexed and abstracted in the SCIE (Science Citation Index Expanded) since Volume 9, Issue 1 in 2009. Furthermore, it continues to maintain its listing in the SCOPUS database and is recognized as a regular journal by the Korea Research Foundation.

※ The user interface design of www.jsts.org has been recently revised and updated. Please contact inter@theieie.org for any inquiries regarding paper submission.

Journal Search

  1. Home
  2. Archive
  3. 2020-02 (Vol.20 No.01)
  4. 10.5573/JSTS.2020.20.1.041
XML PDF INFO REF

REFERENCES

1 
Sakurai T., 2004, Perspectives of low-power VLSI's, IEICE Trans. Electron., Vol. E87-C, No. 4, pp. 429-436Google Search
2 
Nowak E. J., 2002, Maintaining the benefits of CMOS scaling when scaling bogs down, IBM J. Res. Dev., Vol. 46, No. 2.3, pp. 169-180DOI
3 
Wang P. Y., Tsui B. Y., 2016, Band engineering to improve average subthreshold swing by suppressing low electric field band-to-band tunneling with epitaxial tunnel layer tunnel FET structure, IEEE Trans. Nanotechnol., Vol. 15, No. 1, pp. 74-79DOI
4 
Mishra A., Pattanaik M., Sharma V., 2013, Double gate vertical tunnel FET for hybrid CMOS-TFET based low standby power logic circuits, 2013 Annual International Conference on Emerging Research Areas and 2013 International Conference on Microelectronics, Communications and Renewable Energy, pp. 1-4DOI
5 
Cristoloveanu S., Wan J., Zaslavsky A., 2016, A review of sharp-switching devices for ultra-low power applications, IEEE Journal of the Electron Devices SocietyDOI
6 
Ji S., Kim H., Cho I. H., 2018, Characteristics of recess structure tunneling field effect transistor for high on current drivability, J. Semicond. Technol. Sci., Vol. 18, No. 3, pp. 360-366DOI
7 
Choi W. Y., Park B. G., Lee J. D., Liu T. J. K., 2007, Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec, IEEE Electron Device Lett., Vol. 28, No. 8, pp. 743-745DOI
8 
Kim S. W., Kim J. H., Liu T. J. K., Choi W. Y., Park B. G., 2016, Demonstration of L-Shaped Tunnel Field-Effect Transistors, IEEE Trans. Electron Devices, Vol. 63, No. 4, pp. 1774-1778DOI
9 
Kim M., Wakabayashi Y., Nakane R., Yokoyama M., Takenaka M., Takagi S., 2014, High Ion/Ioff Ge-source ultrathin body strained-SOI tunnel FETs, 2014 IEEE International Electron Devices Meeting, pp. 13.2.1-13.2.4.DOI
10 
Kim H. W., Kim J. H., Kim S. W., Sun M. C., Park E., Park B. G., 2014, Tunneling field-effect transistor with Si/SiGe material for high current drivability, Jpn. J. Appl. Phys., Vol. 53, No. 6S, pp. 06JE12-06JE12-4DOI
11 
Moselund K. E., Schmid H., Bessire C., Bjork M. T., Ghoneim H., Riel H., 2012, InAs-Si nanowire heterojunction tunnel FETs, IEEE Electron Device Lett., Vol. 33, No. 10, pp. 1453-1455DOI
12 
Tomioka K., Yoshimura M., Fukui T., 2012, Steep-slope tunnel field-effect transistors using III-V nanowire/Si heterojunction, 2012 Symposium on VLSI Technology (VLSIT), pp. 47-48DOI
13 
Chen Z. X., et al. , 2009, Demonstration of tunneling FETs based on highly scalable vertical silicon nanowires, IEEE Electron Device Lett., Vol. 30, No. 7, pp. 754-756DOI
14 
Conzatti F., Pala M. G., Esseni D., Bano E., Selmi L., 2012, Strain-induced performance improvements in InAs nanowire tunnel FETs, IEEE Trans. Electron Devices, Vol. 59, No. 8, pp. 2085-2092DOI
15 
Wang X., Brown A. R., Cheng B., Asenov A., 2011, Statistical variability and reliability in nanoscale FinFETs, 2011 International Electron Devices Meeting, pp. 5.4.1-5.4.4DOI
16 
Baravelli E., Dixit A., Rooyackers R., Jurczak M., Speciale N., De Meyer K., 2007, Impact of line-edge roughness on FinFET matching performance, IEEE Trans. Electron Devices, Vol. 54, No. 9, pp. 2466-2474DOI
17 
Patel K., Liu T. J. K., Spanos C. J., 2009, Gate line edge roughness model for estimation of FinFET performance variability, IEEE Trans. Electron Devices, Vol. 56, No. 12, pp. 3055-3063DOI
18 
Baravelli E., Jurczak M., Speciale N., De Meyer K., Dixit A., 2008, Impact of LER and random dopant fluctuations on FinFET matching performance, IEEE Trans. Nanotechnol., Vol. 7, No. 3, pp. 291-298DOI
19 
Asenov A., Kaya S., Brown A. R., 2003, Intrinsic parameter fluctuations in decananometer MOSFETs introduced by gate line edge roughness, IEEE Trans. Electron Devices, Vol. 50, No. 5, pp. 1254-1260DOI
20 
Choi W. Y., 2017, Influence of line-edge roughness on multiple-gate tunnel field-effect transistors, Jpn. J. Appl. Phys., Vol. 56, No. 4S, pp. 04CD06DOI
21 
Chen C., Chen Y., Fan M., Hu V. P., Su P., Chuang C., 2014, Impacts of work function variation and line-edge roughness on TFET and FinFET devices and logic circuits, 2014 SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), pp. 1-2DOI
22 
Damrongplasit N., Kim S. H., Shin C., Liu T. J. K., 2013, Impact of gate line-edge roughness (LER) versus random dopant fluctuations (RDF) on germanium-source tunnel FET performance, IEEE Trans. Nanotechnol., Vol. 12, No. 6, pp. 1061-1067DOI
23 
Cheng Y. H., 2019, Comparison of MOSFET threshold voltage extraction methods with temperature variation, IEEE International Conference on Microelectronic Test Structures, pp. 126-131DOI
24 
Synopsys Inc. , 2009, Sentaurus Device User Guide - v.K-2015.06Google Search
25 
Kane E. O., Jan 1961, Theory of tunneling, J. Appl. Phys., Vol. 32, No. 1, pp. 83-91DOI
26 
Terada K., Nishiyama K., Ichi Hatanaka K., 2001, Comparison of MOSFET-threshold-voltage extraction methods, Solid. State. Electron., Vol. 45, No. 1, pp. 35-40DOI
27 
Kim S. W., Choi W. Y., 2016, Hump Effects of Germanium/Silicon Heterojunction Tunnel Field-Effect Transistors, IEEE Trans. Electron Devices, Vol. 63, No. 6, pp. 2583-2588DOI