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Title [REGULAR PAPER] Design Method for Active-shunt-feedback Type Inductorless Low-noise Amplifiers in 65-nm CMOS
Authors Toshiyuki Inoue; Akira Tsuchiya; Keiji Kishine
DOI https://doi.org/10.5573/JSTS.2020.20.2.177
Page pp.177-186
ISSN 1598-1657
Keywords Low-noise amplifier; inductorless; noise cancelling; 65-nm CMOS; wireless sensor network
Abstract We demonstrated low-power and compact active-shunt-feedback type inductorless low-noise amplifiers (LNAs) in 65-nm CMOS. We pointed out the importance of considering an intermediate-node voltage in the LNA, and proposed a design method focusing on the intermediate voltage. The influence of the intermediate voltage upon the gain and noise figure was examined by a circuit simulator, and it was clarified that the intermediate voltage of VDD/2 was appropriate for high gain and low noise figure. Based on the proposed method, the active-shunt-feedback type LNA was fabricated in a 65-nm CMOS chip. The figure-of-merit considering the power, gain, band-width, noise factor, and linearity improved by 6 in comparison with that of the conventional 0.13-?m CMOS type.