1. Circuit Configuration and Operating Principle

A schematic diagram of the fabricated LNA is shown in Fig. 1. This LNA is composed of two CG amplifiers using NMOS (M$_{1}$) and PMOS (M$_{2}$), a common-source (CS) NMOS (M$_{3}$) for active-shunt-feedback, and a capacitor ($\textit{C}$$_{\mathrm{C}}$) between nodes 1 and 2 for noise-cancelling. The feedback transistor works to decrease the input impedance and enlarge the bandwidth. Also, a back-gate voltage for the feedback transistor, $\textit{V}$$_{\mathrm{BG}}$, enables to change the amount of feedback current and adjust the input impedance to source impedance, $\textit{R}$$_{\mathrm{S}}$ (50~$\Omega$ in most cases). The noise voltage at node 3 derived from the noise current of M$_{1}$ and M$_{2}$ is amplified by the other MOSFET. Since the phase of the noise voltage at node 1 is opposite to that at node 2, the coupling capacitor combines the noise voltages of nodes 1 and 2 and can be partially cancelled.

2. Importance of Intermediate-node Voltage

Fig. 2(a) shows a basic structure of the fabricated LNA, where a feedback transistor and a coupling capacitor are removed from the original LNA shown in Fig. 1. As shown in Fig. 2(a), the focused LNA can be considered as the structure stacked with NMOS and PMOS amplifiers vertically. Hence, we can design an NMOS amplifier and a PMOS amplifier separately as shown in Fig. 2(b) and (c), where $\textit{v}$$_{\mathrm{in}}$ is a small-signal voltage source; $\textit{V}$$_{\mathrm{GS}}$$_{i}$, $\textit{V}$$_{\mathrm{DS}}$$_{i}$, and $\textit{V}$$_{\mathrm{DD}}$$_{i}$ are gate-source, drain-source, and supply voltages, respectively; 1 and 2 stand for NMOS (M$_{1}$) and PMOS (M$_{2}$), respectively; $\textit{V}$$_{\mathrm{DD}}$$_{i}$ satisfies $\textit{V}$$_{\mathrm{DD1}}$ + $\textit{V}$$_{\mathrm{DD2}}$ = $\textit{V}$$_{\mathrm{DD}}$. As shown in Fig. 2(a), the drain current drawn by the NMOS and PMOS amplifiers is the almost same. Therefore, the drain current of the amplifiers, $\textit{I}$$_{\mathrm{D}}$, in Fig. 2(b) and (c) should be same so that the operating condition would not be drastically changed after stacking the amplifiers.

An intermediate-node voltage between the NMOS and PMOS amplifiers, $\textit{V}$$_{\mathrm{MID}}$, is related with $\textit{V}$$_{\mathrm{DD1}}$ and $\textit{V}$$_{\mathrm{DD2}}$ as

Although larger $\textit{V}$$_{\mathrm{DD}}$$_{i}$ leads to higher gain of the amplifiers, the trade-off relation between $\textit{V}$$_{\mathrm{DD1}}$ and $\textit{V}$$_{\mathrm{DD2}}$ exists as shown in Eqs. (1a) and (1b). The value of $\textit{V}$$_{\mathrm{MID}}$ may affect not only the LNA gain but also the noise-cancelling effect since a PMOS amplifier works to cancel the generated noise. Therefore, the intermediate-node voltage should be considered carefully for designing the fabricated LNA.

1. Designing NMOS and PMOS Amplifiers

As mentioned in the previous section, we can consider NMOS and PMOS amplifiers separately. Then, we examine the effect the intermediate voltage on the gain of each amplifier.

The input impedance of the basic structure shown in Fig. 2(a) is given by

where $\textit{g}$$_{\mathrm{m}}$$_{i}$ is the transconductance of M$_{i}$, $\textit{g}$$_{\mathrm{o}}$$_{i}$ is the output conductance of M$_{i}$, and $\textit{R}$$_{i}$ is the load resistance for M$_{i}$, respectively. Assume that the value of $\textit{g}$$_{\mathrm{o}}$$_{i}$ is small enough, the input impedance can be expressed approximately as

To satisfy the input matching condition, $\textit{Z}$$_{\mathrm{in}}$ = $\textit{R}$$_{\mathrm{S}}$ = 50~$\Omega$, the total transconductance, $\textit{g}$$_{\mathrm{m1}}$ + $\textit{g}$$_{\mathrm{m2}}$, should have ~20 mS. Therefore, the input impedance is close to the matching condition when each MOSFET has ~10 mS. Note that the input matching condition does not need to be satisfied strictly in this step since a feedback transistor will be added to this structure later.

To evaluate the dependence of the intermediate-node voltage upon the characteristics of the amplifiers, we considered three cases: (i) $\textit{V}$$_{\mathrm{MID}}$ > $\textit{V}$$_{\mathrm{DD}}$/2, (ii) $\textit{V}$$_{\mathrm{MID}}$ = $\textit{V}$$_{\mathrm{DD}}$/2, and (iii) $\textit{V}$$_{\mathrm{MID}}$ < $\textit{V}$$_{\mathrm{DD}}$/2. The gate-source voltage, $\textit{V}$$_{\mathrm{GS}}$$_{i}$, was set for $\textit{g}$$_{\mathrm{m}}$$_{i}$ = 10 mS, and the load resistance for each amplifier was determined as

The characteristics of the amplifiers were examined by using circuit simulators (HSPICE and Spectre) with the parameters of the TSMC 65-nm CMOS process. The supply voltage was set to $\textit{V}$$_{\mathrm{DD}}$ = 1.2 V; $\textit{V}$$_{\mathrm{DD1}}$ and $\textit{V}$$_{\mathrm{DD2}}$ were set to 0.5 V and 0.7 V for the case (i), 0.6 V and 0.6~V for the case (ii), and 0.7 V and 0.5 V for the case (iii), respectively.

Figs. 3-5 show the dependences of the approximate voltage gain calculated from $\textit{g}$$_{\mathrm{m}}$$_{i}$$\textit{R}$$_{i}$ upon drain current for each case, where the filled and open symbols signify the results of NMOS and PMOS amplifiers, respectively. The data of MOSFETs operating in a saturation region are shown in Figs. 3-5. Reducing the drain current corresponds to increasing the gate width since $\textit{g}$$_{\mathrm{m}}$$_{i}$ is fixed at 10 mS. In the case (i) shown in Fig. 3, the gains of NMOS and PMOS amplifiers are the highest at |$\textit{V}$$_{\mathrm{DS1}}$| = 0.20 V and |$\textit{V}$$_{\mathrm{DS2}}$| = 0.25 V, respectively. The gain of PMOS is higher than that of NMOS by ~1 dB for every $\textit{I}$$_{\mathrm{D}}$. In the case (ii) shown in Fig. 4, the highest gains are obtained by setting |$\textit{V}$$_{\mathrm{DS}}$$_{i}$| = 0.20 V. The gain of NMOS amplifier is higher than that of PMOS by ~1 dB. In the case (iii) as shown in Fig. 5, the gains of NMOS and PMOS amplifiers are the highest at |$\textit{V}$$_{\mathrm{DS1}}$| = 0.25 V and |$\textit{V}$$_{\mathrm{DS2}}$| = 0.20 V, respectively. The gain of NMOS amplifier is higher than that of PMOS, and the gain difference is ~4 dB, which is larger than that for cases (i) and (ii). From these results, we found that the intermediate-node voltage affected the gain of NMOS and PMOS amplifiers, and that the drain-source voltage to maximize the gain existed for each $\textit{V}$$_{\mathrm{DD}}$$_{i}$.

2. Analysis of Stacked Structure

Fig. 3. Dependence of voltage gain, $\textit{g}$$_{\mathrm{m}}$$_{i}$$\textit{R}$$_{i}$, upon drain current for case (i): $\textit{V}$$_{\mathrm{DD1}}$ = 0.5 V, $\textit{V}$$_{\mathrm{DD2}}$ = 0.7 V.

Fig. 4. Dependence of voltage gain, $\textit{g}$$_{\mathrm{m}}$$_{i}$$\textit{R}$$_{i}$, upon drain current for case (ii): $\textit{V}$$_{\mathrm{DD1}}$ = 0.6 V, $\textit{V}$$_{\mathrm{DD2}}$ = 0.6 V.

We examined the characteristics of the stacked structure shown in Fig. 2(a). Based on the analyses shown in Figs. 3-5, the parameters of $\textit{V}$$_{\mathrm{GS}}$$_{i}$, $\textit{R}$$_{i}$, and the gate width of M$_{i}$ were chosen so that the NMOS and PMOS amplifiers could draw almost the same current. Then, the NMOS and PMOS amplifiers using the obtained parameters were stacked. Here, the intermediate voltage, $\textit{V}$$_{\mathrm{MID}}$, is almost as same as $\textit{V}$$_{\mathrm{DD2}}$. The drain current was set to 0.8 mA to obtain higher gain and operation in 2.4-GHz band. The load capacitance of the amplifier was set to 100 fF. Fig. 6 shows the voltage gains, $\textit{v}$$_{\mathrm{out}}$$_{i}$$_{\mathrm{/}}$$\textit{v}$$_{\mathrm{in}}$, against the frequency for each intermediate-node voltage, where the solid and dashed lines signify $\textit{v}$$_{\mathrm{out1/}}$$\textit{v}$$_{\mathrm{in}}$ (NMOS amplifier side) and $\textit{v}$$_{\mathrm{out2/}}$$\textit{v}$$_{\mathrm{in}}$ (PMOS amplifier side), respectively; the blue, red, and green lines signify the results of $\textit{V}$$_{\mathrm{MID}}$ = 0.7, 0.6, 0.5 V, respectively. The intermediate-node voltages, $\textit{V}$$_{\mathrm{MID}}$ = 0.7, 0.6, 0.5 V, correspond to the cases (i), (ii), and (iii) in the previous subsection, respectively. As shown in Fig. 6, the magnitude relation between the gains of the NMOS and PMOS amplifiers has good agreement with that of the results shown in Figs. 3-5. The obtained bandwidth is around 3 GHz, which is enough for the 2.4-GHz-band applications.

3. Adding Feedback Transistor and Adjusting Input Impedance

Fig. 5. Dependence of voltage gain, $\textit{g}$$_{\mathrm{m}}$$_{i}$$\textit{R}$$_{i}$, upon drain current for case (iii): $\textit{V}$$_{\mathrm{DD1}}$ = 0.7 V, $\textit{V}$$_{\mathrm{DD2}}$ = 0.5 V.

Fig. 6. Voltage gain, $\textit{v}$$_{\mathrm{out}}$$_{i}$/$\textit{v}$$_{\mathrm{in}}$, against frequency after stacking NMOS and PMOS amplifiers.

As shown in Fig. 7(a), we add a feedback transistor (M$_{3}$) to the previous structure. The gate terminal of the feedback transistor is connected to the output terminal of the PMOS amplifier, and the transistor draws feedback current from the intermediate node. In this structure, the feedback current is reused by the NMOS amplifier, therefore it leads to reducing power consumption.

The input impedance can be rewritten by

where $\textit{g}$$_{\mathrm{m3}}$ and $\textit{g}$$_{\mathrm{o3}}$ are the transconductance and output conductance of the feedback transistor, respectively. In comparison with Eq. (2), the input impedance can be decreased by the effect of the feedback transistor as shown in the third and fourth terms of Eq. (5).

Fig. 7. Schematic diagram after adding feedback transistor and coupling capacitor to basic structure.

Fig. 8. Frequency response of input impedance. Dashed and solid lines signify results without and with feedback, respectively.

Fig. 8 shows the frequency response of the input impedance in the case (ii) ($\textit{V}$$_{\mathrm{MID}}$ = 0.6 V), where $\textit{W}$ is the gate width of the feedback transistor, dashed line and solid lines signify the results without and with the feedback, respectively. Although the impedance without the feedback is slightly higher than the matching condition, the matching condition can be satisfied by adding the transistor with appropriate gate width ($\textit{W}$ = 8~μm). The intermediate voltage corresponds to the gate voltage of M$_{3}$, the gate width of the case (i) or (iii) should be smaller or larger than that of the case (ii) to satisfy the matching condition, respectively.

Fig. 9. NF and $\textit{S}$$_{21}$ against coupling capacitance. Solid and dashed lines signify results of NF and $\textit{S}$$_{21}$, respectively.

Fig. 10. Frequency response of NF. Dashed and solid lines signify results without and with capacitor of 2 pF, respectively.

4. Adding Coupling Capacitor and Examining Noise-Cancelling Effect

As shown in Fig. 7(b), we add a coupling capacitor ($\textit{C}$$_{\mathrm{C}}$) to the basic structure. To evaluate $\textit{S}$-parameters and noise figure (NF), a buffer circuit (CS amplifier) with a 0-dB gain for the output matching is connected in this simulation. Fig. 9 shows the simulation results of NF (solid lines) and $\textit{S}$$_{21}$ (dashed lines) against the coupling capacitance for each $\textit{V}$$_{\mathrm{MID}}$ at 2.4 GHz, where the blue, red, and green lines signify the results of $\textit{V}$$_{\mathrm{MID}}$ = 0.7, 0.6, 0.5 V, respectively. The NF is reduced as the capacitance is increased. Although larger capacitance is required to obtain lower NF, increasing the capacitance results in occupying large chip area. Then, we chose 2 pF from the viewpoint of both reducing NF and saving chip area.

Fig. 10 shows the frequency response of NF without the capacitor (dashed lines) and with the capacitor (solid lines). Although the NF without the coupling capacitor was around 10 dB, the obtained NF was reduced to around 6 dB by adding the capacitor of 2 pF. As shown in Fig. 10, lower NF can be achieved by setting $\textit{V}$$_{\mathrm{MID}}$ = 0.6 V over the entire frequency band.

5. Effect of Back-gate Voltage

Fig. 11. Dependences of $\textit{S}$-parameters upon back-gate voltage, $\textit{V}$$_{\mathrm{BG}}$. Solid and dashed lines signify results of $\textit{S}$$_{11}$ and $\textit{S}$$_{21}$, respectively.

Fig. 12. Dependences of NF upon back-gate voltage, $\textit{V}$$_{\mathrm{BG}}$.

Fig. 13. Linearity of proposed LNA. Solid and dashed lines signify fundamental and IM3 powers, respectively.

We examined the effect of the back-gate voltage of the feedback transistor (M$_{3}$). The simulation results of $\textit{S}$-parameters against the back-gate voltage are shown in Fig. 11, where solid and dashed lines signify the results of $\textit{S}$$_{11}$ and $\textit{S}$$_{21}$, respectively. As shown in Fig. 11, the value of $\textit{S}$$_{11}$ can be minimized by adjusting the back-gate voltage. The value of $\textit{S}$$_{21}$ is increased as the back-gate voltage is decreased, it reaches ~8 dB under $\textit{S}$$_{11}$ < ${-}$20 dB at $\textit{V}$$_{\mathrm{BG}}$ = ${-}$0.5 V in the case (ii). Therefore, we can adjust the input impedance or the gain by changing the back-gate voltage.

We also examined the effect of the back-gate voltage upon the noise characteristics. Fig. 12 shows the simulation results of NF against $\textit{V}$$_{\mathrm{BG}}$ for $\textit{V}$$_{\mathrm{MID}}$ = 0.7, 0.6, 0.5 V. As shown in Fig. 11 and 12, lower NF is obtained by decreasing $\textit{V}$$_{\mathrm{BG}}$ although $\textit{S}$$_{11}$ gets worse. This is because the noise matching condition is slightly different from the impedance matching condition.

6. Linearity Characteristics

We examined the linearity of the proposed LNA by calculating the fundamental and third order intermodulated (IM3) component powers around 2.4 GHz. Fig. 13 shows the output fundamental and IM3 component powers against input power. This result shows that the highest input-referred third-order intercept point (IIP3) is obtained in the case of $\textit{V}$$_{\mathrm{MID}}$ = 0.7 V. However, the gain ($\textit{S}$$_{21}$) and NF for $\textit{V}$$_{\mathrm{MID}}$ = 0.6 V are better than that for $\textit{V}$$_{\mathrm{MID}}$ = 0.7 V as shown in Fig. 9. Also, the output-referred IP3 (OIP3) of $\textit{V}$$_{\mathrm{MID}}$ = 0.6 V is same as large as that of $\textit{V}$$_{\mathrm{MID}}$ = 0.7 V.