| Title |
Probabilistic based CMOS Adder for High Speed Communication Systems |
| Authors |
(S. Venkatesh Babu) ; (S. Arumugam) |
| DOI |
https://doi.org/10.5573/JSTS.2021.21.2.085 |
| Keywords |
Carry propagation path; communication systems; low power design; probabilistic approach; acceptable accuracy |
| Abstract |
Power efficient is an important availability for various mobile devices and communication system applications. The proposed probabilistic adder is to trade a lesser amount of accuracy with reduced power dissipation. In this paper, the probabilistic adder is eliminating the some part of the carry propagation path in least significant bit to reduce the power consumption and transistor count. The power consumption and probabilistic error behaviour of the proposed adder is designed and compared with other adders. |