Title |
Body-biasing-based Latch Offset Cancellation Sensing Circuit for Deep Submicrometer STT-MRAM |
DOI |
https://doi.org/10.5573/JSTS.2021.21.2.126 |
Keywords |
Body-biasing; latch offset cancellation; positive feedback; sensing circuit; resistive device; spin-transfer-torque magnetoresistive random access memory (STT-MRAM). |
Abstract |
Even though spin-transfer-torque magnetoresistive random access memory (STT-MRAM) is considered to be a leading candidate for next generation memory, designing a sensing circuit (SC) that achieves sufficient read yield is challenging because of the increased process variation, decreased read current (Iread), and small tunnel magneto-resistance (TMR) ratio. In this paper, a novel body-biasing-based latch offset cancellation SC (BBLOC-SC) that is capable of canceling the offset voltage caused by the latch sense amplifier is proposed. Monte Carlo HSPICE simulation results using industry-compatible 28-nm model parameters show that the proposed BBLOC-SC achieves a much higher read yield compared to the state-of-the-art SCs, regardless of TMR and Iread. |