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“JSTS has been indexed and abstracted in the SCIE (Science Citation Index Expanded) since Volume 9, Issue 1 in 2009. Furthermore, it continues to maintain its listing in the SCOPUS database and is recognized as a regular journal by the Korea Research Foundation.

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REFERENCES

1 
Hosomi M., 2005, A novel nonvolatile memory with spin torque transfer magnetization switching: Spin-RAM, In Proc. IEEE Int. Electron Devices Meeting (IEDM) Tech. Dig., Vol. , No. , pp. 459-462DOI
2 
Lin C. J., 2009, 45 nm low power CMOS logic compatible embedded STT MRAM utilizing a reverse-connection 1T/1MTJ cell, in IEEE Int. Electron Devices Meeting (IEDM) Tech. Dig., pp. 279-282DOI
3 
Tsuchida K., 2010, A 64Mb MRAM with clamped-reference and adequate-reference schemes, in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, pp. 258-259DOI
4 
Ikeda S., Jul 2010, A perpendicular-anisotropy CoFeB-MgO magnetic tunnel junction, Nature Materials, pp. 721-724DOI
5 
Kang S. H., Lee K., 2013, Emerging materials and devices in spintronic integrated circuits for energy-smart mobile computing and connectivity, Acta Materialia, Vol. 61, No. 3, pp. 952-973DOI
6 
Na T., Jan 2021, STT-MRAM sensing: a review, IEEE Trans. Circuits Syst. II Exp. Briefs, Vol. 68, No. 1, pp. 12-18DOI
7 
Kang S. H., Park C., 2017, MRAM: enabling a sustainable device for pervasive system architectures and applications, in IEEE Int. Electron Devices Meeting (IEDM) Tech. Dig., pp. 38.2.1-38.2.4DOI
8 
Wei L., 2019, A 7Mb STT-MRAM in 22FFL FinFET technology with 4ns read sensing time at 0.9V using write-verify-write scheme and offset-cancellation sensing technique, in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, pp. 214-215DOI
9 
Chih Y.-D., 2020, A 22nm 32Mb embedded STT-MRAM with 10ns read speed, 1M cycle write endurance, 10 years retention at 150$^\circ$C and high immunity to magnetic field interference, in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, pp. 222-224DOI
10 
Lu Y., 2015, Fully functional perpendicular STT-MRAM macro embedded in 40 nm logic for energy-efficient IOT applications, In Proc. IEEE Int. Electron Devices Meeting (IEDM) Tech. Dig., pp. 26.1.1-26.1.4DOI
11 
Kim C., 2015, A covalent-bonded cross-coupled current-mode sense amplifier for STT-MRAM with 1T1MTJ common source-line structure array, in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, pp. 1-3DOI
12 
Rizzo N., 2010, Toggle and spin torque: MRAM at Everspin technologies, Non-volatile Memories WorkshopGoogle Search
13 
Rizzo N. D., Jul 2013, A fully functional 64 Mb DDR3 ST-MRAM built on 90 nm CMOS technology, IEEE Trans. Magn., Vol. 49, No. 7, pp. 4441-4446DOI
14 
Lee K., Kang S. H., Jan 2011, Development of embedded STT-MRAM for mobile system-on-chips, IEEE Trans. Magn., Vol. 47, No. 1, pp. 131-136DOI
15 
Kim J. P., 201, A 45nm 1Mb embedded STT-MRAM with design techniques to minimize read-disturbance, in IEEE Symp. VLSI Circuits Dig. Tech. Papers1, pp. 296-297Google Search
16 
Kim J., Jan 2012, A novel sensing circuit for deep submicron spin transfer torque MRAM (STT-MRAM), IEEE Trans. Very Large Scale Integr. (VLSI) Syst., Vol. 20, No. 1, pp. 181-186DOI
17 
Ren F., 2012, A body-voltage-sensing-based short pulse reading circuit for spin-torque transfer RAMs (STT-RAMs), in Int. Symp. Quality Electron Design (ISQED), pp. 275-282DOI
18 
Kim J., Jul 2014, STT-MRAM sensing circuit with self-body biasing in deep submicron technologies, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., Vol. 22, No. 7, pp. 1630-1634DOI
19 
Yang L., May 2015, A body-biasing of readout circuit for STT-RAM with improved thermal reliability, in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), pp. 1530-1533DOI
20 
Na T., Woo S.-H., Kim J., Jeong H., Jung S.-O., Feb 2014, Comparative study of various latch-type sense amplifiers, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., Vol. 22, No. 2, pp. 425-429DOI