Mobile QR Code QR CODE

“JSTS has been indexed and abstracted in the SCIE (Science Citation Index Expanded) since Volume 9, Issue 1 in 2009. Furthermore, it continues to maintain its listing in the SCOPUS database and is recognized as a regular journal by the Korea Research Foundation.

※ The user interface design of www.jsts.org has been recently revised and updated. Please contact inter@theieie.org for any inquiries regarding paper submission.

Journal Search

  1. Home
  2. Archive
  3. JSTS 2021-06(Vol.21 No.03)
XML PDF INFO REF
Title Neural Spike Detection Circuit with Amplification Method using Input DC Level Control
Authors (Jong Pal Kim)
DOI https://doi.org/10.5573/JSTS.2021.21.3.183
Page pp.183-188
ISSN 1598-1657
Keywords Electroceuticals; implantable device; neural spike; IA; instrumentation amplifier
Abstract A neural spike detection circuit is presented, in which all the amplifiers have an open loop architecture to reduce area and current consumption fundamentally. A new method for controlling the gain of an open loop amplifier is proposed. The gains of instrumentation amplifier (IA) and multiplier are controlled by a DC level of the input. In addition, an instrumentation amplifier (IA) includes a compensation circuit against the fabrication process corners to prevent amplification failure. The compensation circuit detects and adds threshold voltage variations in the compensation feedback loop. The circuit is fabricated using the standard 0.18 μm CMOS process. Changing the DC level at the IA input results in the amplification gain increase up to 650 V/V. The nonlinear amplification control capability of the multiplier is verified as the DC input level changes. The minimum detectable amplitude of neural spike is 100 μVpk. The overall power consumption is 1.4 μW. Integrated input-referred noise is measured to be 7.1 μVrms in a frequency range of 100 Hz to 10 kHz.