| Title |
A 32.2 GHz Full Adder Designed with TLE Method in a InP DHBT Technology |
| Authors |
(Yi Zhang) ; (Xiaopeng Li) ; (Youtao Zhang) ; (Yufeng Guo) ; (Ying Zhang) ; (Hao Gao) |
| DOI |
https://doi.org/10.5573/JSTS.2021.21.6.438 |
| Keywords |
Full adder; carry; InP DHBT; signal integrity; TLE mthod |
| Abstract |
Ultra-high-speed full adder is the bottleneck in a tens of GHz Direct digital synthesizer (DDS). In this paper, a 32.2 GHz, 1bit full adder in a 0.7 μm InP double hetero-junction bipolar transistor (DHBT) technology is presented. In such a high-speed circuit, signal integrity is a crucial issue. Therefore, a transmission line equivalent (TLE) method is proposed. With the TLE method, the design of the full adder could be simplified with good accuracy. The synchronous latch is combined with adding operation to improve the calculation speed. A single-level parallel-gated circuit is designed using majority decision algorithm to reduce power consumption. Measurement results show that the maximum clock frequency of the full adder is 32.2-GHz, and the overall power consumption is 350 mW. The full adder is successfully adopted in a 17 GHz, 8 bit DDS which can synthesize sin-wave outputs from 66.41 MHz to 8.5 GHz in 66.41 MHz steps with an average Spurious-Free Dynamic Range (SFDR) of -18.1 dBc. |