| Title |
A 70 dB SNDR 10 MS/s 28 nm CMOS Nyquist SAR ADC with Capacitor Mismatch Calibration Reusing Segmented Reference Voltages |
| Authors |
(Ho-Jin Kim) ; (Jun-Ho Boo) ; (Jae-Hyuk Lee) ; (Jun-Sang Park) ; (Tai-Ji An) ; (Sung-Han Do) ; (Young-Jae Cho) ; (Michael Choi) ; (Gil-Cho Ahn) ; (Seung-Hoon Lee) |
| DOI |
https://doi.org/10.5573/JSTS.2021.21.6.449 |
| Keywords |
Analog-to-digital converter (ADC); successive-approximation register (SAR); capacitor calibration; low-noise comparator |
| Abstract |
This paper proposes a calibrated 14-bit 10 MS/s 28 nm CMOS Nyquist successive-approximation register (SAR) analog-to-digital converter (ADC). The upper 9 bits and the remaining lower 5 bits are determined, respectively, using a binary-weighted capacitor array and segmented reference voltages divided from a simple resistor string. While the proposed calibration is applied only to the critical most significant 4-bit capacitors, the segmented reference voltages to decide the lower 5 bits are reused via a unit capacitor. This creates a small weight on the calibration digital-to-analog converter (DAC) in place of making an adjustment to the small-sized actual capacitor value. The proposed calibration does not require extra capacitors smaller than the unit capacitor, reducing the chip area and circuit complexity. The comparator employs a noise-reduction capacitor, enabling it to realize low-noise performance with low-power. The prototype ADC in a 28 nm CMOS occupies an active die area of 0.062 mm2 and consumes 351 μW at a 1.0 V supply voltage. After calibration, the prototype ADC shows a measured differential non-linearity (DNL) and integral non-linearity (INL) within 1.59 LSB and 2.92 LSB, respectively, at 14 bits with a maximum signal-to-noise-and-distortion ratio (SNDR) and spurious-free dynamic range (SFDR) of 70.0 dB and 85.0 dB at 10 MS/s, respectively. |