1. Proposed SAR ADC Architecture

The overall structure of the proposed 14-bit 10 MS/s 28 nm CMOS SAR ADC is shown in Fig. 1. It is composed of a capacitor-resistor (C-R) hybrid DAC with a calibration scheme, a comparator, a SAR logic, a calibration logic, and control and timing circuits. The proposed C-R hybrid DAC with common-mode voltage (VCM)-based switching determines the upper 9 bits using the binary-weighted capacitor array. The remaining lower 5 bits are determined by using the unit capacitors and the reusable segmented reference voltages divided from a simple binary-weighted resistor string ^(18,19). Since only 520 unit capacitors are used to implement a 14-bit DAC, the proposed DAC structure can reduce the number of unit capacitors required.

In the C-R hybrid DAC, the unit capacitance is determined to be 10fF based on the input signal range of 2.0V$_{\mathrm{P-P}}$, kT/C noise, and capacitor matching characteristics ^(1,2). The resistor string used to determine the lower 5 bits has a binary-weighting structure. The capacitor calibration is applied to the uppermost 4 capacitors -128$C_{\mathrm{U}}$, 64$C_{\mathrm{U}}$, 3$2C_{\mathrm{U}}$, and 16$C_{\mathrm{U}}$ -which have the biggest impact on the linearity of the capacitor array, minimizing performance degradation that may result from capacitor mismatch. The proposed calibration scheme, instead of using an additional calibration DAC or a custom calibration capacitor smaller than the unit capacitor, reuses the segmented reference voltages, reducing the complexity of the calibration circuit. The comparator with noise-reduction capacitors is employed not only to determine the 14-bit digital code during SAR operation but also to measure the abnormality of the capacitor array during calibration.

Fig. 2. Flow chart of the proposed capacitor algorithm.

Fig. 3. Implementation example of the proposed capacitor calibration.

The resistor string used to determine the lower 5 bits has a binary-weighting structure. The segmented reference voltages are not highly accurate due to mismatches between resistors. These non-ideal reference segment voltages can affect the linearity of the C-R hybrid DAC. However, the non-ideal components of the resistor string are attenuated at the DAC output by a ratio of the unit capacitance to the total capacitance of the DAC. As a result, the required matching accuracy of the resistor string is reduced to approximately 7 bits ⁽¹⁹⁾. Meanwhile, since the resistance of the R-DAC determines the current between VREF+ and VREF-, it affects the settling behavior of the reference voltages. Given the required accuracy and the settling time of the segmented reference voltages, a unit resistance of 400Ω is used. Based on Monte Carlo simulation, the estimated matching accuracy of the designed resistor string for the given process satisfies over 7 bits, which meets the required matching accuracy sufficiently. In addition, since the noise of the resistor string is also attenuated at the DAC output, it hardly contributes to the performance degradation of the entire C-R hybrid DAC.

The glitches in the reference voltages due to R-DAC switching kickback noise occur periodically. During the lower 5-bit conversion cycles using R-DAC, the reference voltages are only connected to the 10fF unit capacitor through the resistor ladder, so the glitch size of the reference voltages are small and the reference voltages stabilize within a given time.

2. Proposed Capacitor Calibration Scheme

The flow chart of the capacitor calibration algorithm is shown in Fig. 2. The proposed capacitor calibration scheme is applied to the most significant 4-bit capacitors. The calibration target capacitors are assigned in order from the fourth uppermost capacitor, 16$C_{\mathrm{U}}$, where N is 0, to the first uppermost capacitor, 128$C_{\mathrm{U}}$, where N is 3. The objective for calibration is to transform the DAC into an ideal binary-weighted capacitor array. The difference, E, between the capacitance of the calibration target capacitor, $2^{N+4}$$C_{\mathrm{U}}$, and the total summed capacitance of the lower capacitors, $\sum _{\mathrm{k}=0}^{3- \mathrm{N}}2^{\mathrm{k}}C_{\mathrm{U}}$ + $C_{\mathrm{U}}$, is compared. Depending on the comparison result, the value of $2^{N+4}$$C_{\mathrm{U}}$ is adjusted to be bigger or smaller. The implementation example, where N is 0 or 1, is shown in Fig. 3, respectively.

Fig. 4 shows the procedure for the proposed capacitor calibration in a simplified single-ended version where the calibration target capacitor is 16$C_{\mathrm{U}}$. As shown in Fig. 4(a), during the reference sampling phase, 16$C_{\mathrm{U}}$ and the lower capacitors sample the complementary reference voltages each other, and all upper capacitors than 16$C_{\mathrm{U}}$ are reset. Then, the capacitance of the calibration target capacitor and the total summed capacitance of the lower capacitors are compared during the comparator decision phase. Depending on the comparison result, the capacitance of the calibration target capacitor is adjusted using the combination of external digital codes, $D_{\mathrm{X}}$<2:0>, as shown in Fig. 4(b).

Fig. 4. Capacitor calibration procedure (a) reference sampling, comparator decision, (b) variable capacitor adjustment.

Fig. 5. Conventional calibration circuit based on custom-built capacitors.

Fig. 6. Proposed calibration circuit based on reusable segmented reference voltages.

1. Calibration Reusing Segmented Reference Voltages

Fig. 5 and 6 show the calibration circuit based on a capacitor array. When the calibration target is the k-th weighted capacitor, assume that $C_{\mathrm{N,k}}$ = (1/2)·$C_{\mathrm{U}}$ is a parasitic component of the ideal capacitance, $2^{\mathrm{k}}$$C_{\mathrm{U}}$, and the target capacitor is connected to the reference voltage VREF-. In the conventional capacitor calibration scheme, as shown in Fig. 5, the complementary reference voltage, VREF+, will be connected to the additional custom-built capacitor (1/2)·$C_{\mathrm{U}}$ in the calibration capacitor array to compensate for the non-ideal value of the calibration target capacitor.

In the proposed calibration scheme, as shown in Fig. 6, the non-ideal value can be compensated for by connecting (1/2)·VREF+ to the unit capacitor in the calibration capacitor array. The proposed calibration circuit in this work does not need extra custom-built capacitors and the calibration capacitor array can be laid out together with the sampling capacitor array, reducing the required chip area and the circuit complexity. The expected maximum mismatch range is determined based on the Monte Carlo simulated maximum capacitor mismatch range, the parasitic components between the adjacent capacitors, and the design margin.

2. Low-noise Comparator with a Noise-reduction Capacitor

Fig. 7. Low-power low-noise comparator with noise-reduction capacitor.

Fig. 8. Simulated power consumption and noise performance of the comparator corresponding to noise-reduction capacitor.

Fig. 9. Layout and die photo of the prototype ADC.

Fig. 10. (a) Power distribution, (b) noise contribution of the prototype ADC.

To apply the proposed calibration scheme, it is necessary to have a process to compare the capacitance of the calibration target capacitor and the sum of the lower capacitors. For this process, a low-noise comparator with 14-bit accuracy is required. As shown in Fig. 7, the proposed SAR ADC employs a noise-reduction capacitor-based comparator. The proposed comparator attenuates noise using the noise-reduction capacitors, $C_{\mathrm{LP}}$ and $C_{\mathrm{LN}}$, connected to the first-stage latch output terminals ⁽²⁰⁾. The simulated noise performance and power consumption of the proposed comparator corresponding to the noise-reduction capacitor is shown in Fig. 8. In the proposed comparator, given the required noise performance, power consumption, and chip area, both $C_{\mathrm{LP}}$ and $C_{\mathrm{LN}}$ are selected to be 400 fF.