| Title |
Study on Low-jitter and Low-power PLL Architectures for Mobile Audio Systems |
| Authors |
(Yujin Kyung) ; (Gwang Sub Kim) ; (Donghyun Baek) |
| DOI |
https://doi.org/10.5573/JSTS.2022.22.6.482 |
| Keywords |
Clock generator; phase-locked loop (PLL); low jitter; phase noise; multiplying delay locked loop (MDLL); sub-sampling PLL (SSPLL); reference-sampling PLL (RSPLL) |
| Abstract |
This paper compares four phase-locked loops (PLLs) for mobile audio applications. We compare and analyze PLL structures and discuss the optimized PLL structure in the audio band frequency. A charge-pump-based integer-N PLL (NPLL) is employed as a reference. To improve the jitter performances, multiplying delay-locked loop (MDLL), sub-sampling PLL (SSPLL), and reference-sampling PLL (RSPLL) are employed and analyzed. The frequency range of the PLLs is from 8 MHz to 71.5 MHz. These PLL chips are fabricated using a Samsung 0.13-?m CMOS process. The resulting figures-of-merit for the NPLL, MDLL, SSPLL, and RSPLL are ?204.3, ?211.07, ?220.29, and ?213.32 dB, respectively, at 24.576 MHz. The total power consumption from a 1.5-V supply voltage is 1.82, 1.35, 1.43, and 1.64 mW, respectively. |