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“JSTS has been indexed and abstracted in the SCIE (Science Citation Index Expanded) since Volume 9, Issue 1 in 2009. Furthermore, it continues to maintain its listing in the SCOPUS database and is recognized as a regular journal by the Korea Research Foundation.

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  4. 10.5573/JSTS.2022.22.6.482
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References

1 
2015, Inter-IC Sound Bus (I2S) 2.70 component datasheet, Infineon, Neubiberg, GermanyGoogle Search
2 
Crawford J. A., 1994, Frequency Synthesizer Design Handbook, Boston, MA: Artech HouseGoogle Search
3 
Santiccioli Alessio, et al , Nov. 2019, A 1.6-to-3.0-GHz Fractional-N MDLL With a Digital-to-Time Converter Range-Reduction Technique Achieving 397-fs Jitter at 2.5-mW Power, IEEE Journal of Solid-State Circuits, Vol. 54, No. 11, pp. 3149-3160DOI
4 
Santiccioli Alessio, et al , Dec. 2020, A 66-fs-rms jitter 12.8-to-15.2-GHz fractional-N bang-bang PLL with digital frequency-error recovery for fast locking, IEEE Journal of Solid-State Circuits, Vol. 55, No. 12, pp. 3349-3361DOI
5 
Zhang Zhao, Zhu Guang, Patrick Yue C., Jun. 2020, A 0.65-V 12-16-GHz sub-sampling PLL with 56.4-fs rms integrated jitter and${-}$ 256.4-dB FoM, IEEE Journal of Solid-State Circuits, Vol. 55, No. 6, pp. 1665-1683DOI
6 
Elkholy Ahmed, et al , Jun. 2018, Low-jitter multi-output all-digital clock generator using DTC-based open loop fractional dividers, IEEE Journal of Solid-State Circuits, Vol. 53, No. 6, pp. 1806-1817DOI
7 
Farjad-Rad Ramin, et al , Dec. 2002, A low-power multiplying DLL for low-jitter multigigahertz clock generation in highly integrated digital chips, IEEE Journal of Solid-State Circuits, Vol. 37, No. 12, pp. 1804-1812DOI
8 
Mercandelli Mario, et al , Feb. 2020, A 12.5-GHz fractional-N type-I sampling PLL achieving 58-fs integrated jitter, IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, pp. 274-276DOI
9 
Kim Juyeop, et al , Dec. 2019, An ultra-low-jitter, mmW-band frequency synthesizer based on digital subsampling PLL using optimally spaced voltage comparators, IEEE Journal of Solid-State Circuits, Vol. 54, No. 12, pp. 3466-3477DOI
10 
Liao Dongyi, et al , Mar, 2018, A 2.4-GHz 16-phase sub-sampling fractional-N PLL with robust soft loop switching, IEEE Journal of Solid-State Circuits, Vol. 53, No. 3, pp. 715-727DOI
11 
Seol Ji-Hwan, et al , Oct. 2021, Reference oversampling PLL achieving${-}$ 256-dB FoM and${-}$ 78-dBc reference spur, IEEE Journal of Solid-State Circuits, Vol. 56, No. 10, pp. 2993-3007DOI
12 
Liao Dongyi, Dai Fa Foster , Mar. 2021, A fractional-N reference sampling PLL with linear sampler and CDAC based fractional spur cancellation, IEEE Journal of Solid-State Circuits, Vol. 56, No. 3, pp. 694-704DOI
13 
Gao Xiang, et al , Dec. 2009, A low noise sub-sampling PLL in which divider noise is eliminated and PD/CP noise is not multiplied by N$^{2}$, IEEE Journal of Solid-State Circuits, Vol. 44, No. 12, pp. 3253-3263DOI
14 
Sharma J., Krishnaswamy H., May 2019, A 2.4-GHz reference-sampling phase-locked loop that simultaneously achieves low-noise and low-spur performance, IEEE Journal of Solid-State Circuits, Vol. 54, No. 5, pp. 1407-1424DOI
15 
Raj Mayank, et al , Jun. 2017, A 164fsrms 9-to-18GHz sampling phase detector based PLL with in-band noise suppression and robust frequency acquisition in 16nm FinFET, 2017 Symposium on VLSI Circuits. IEEE, pp. 182-183DOI
16 
Dai Liang, Harjani Ramesh , 2001, A low-phase-noise CMOS ring oscillator with differential control and quadrature outputs, Proceedings 14th Annual IEEE International ASIC/SOC Conference (IEEE Cat. No. 01TH8558). IEEE, pp. 113-118DOI
17 
Elshazly Amr, et al , Jun. 2013, Clock multiplication techniques using digital multiplying delay-locked loops, IEEE Journal of Solid-State Circuits, Vol. 48, No. 6, pp. 1416-1428DOI
18 
Sharma J., 2018, CMOS signal synthesizers for emerging RF-to-optical applications, Columbia UniversityURL
19 
Elshazly Amr, et al , Jun. 2013, Clock multiplication techniques using digital multiplying delay-locked loops, IEEE Journal of Solid-State Circuits, Vol. 48, No. 6, pp. 1416-1428DOI