| Title |
An 11-bit 160-MS/s Non-binary C-based SAR ADC with a Partially Monotonic Switching Scheme |
| Authors |
(Jae-Hyuk Lee) ; (Jun-Ho Boo) ; (Jun-Sang Park) ; (Tai-Ji An) ; (Hee-Wook Shin) ; (Young-Jae Cho) ; (Michael Choi) ; (Jin-Wook Burm) ; (Gil-Cho Ahn) ; (Seung-Hoon Lee) |
| DOI |
https://doi.org/10.5573/JSTS.2023.23.2.118 |
| Keywords |
Analog-to-digital converter (ADC); non-binary digital-to-analog converter (DAC); partially monotonic switching; redundancy; successive-approximation register (SAR) |
| Abstract |
This work proposes a single-channel 11-bit successive-approximation register (SAR) analog-to-digital converter (ADC) with an operating speed of 160-MS/s based on a non-binary digital-to-analog converter (DAC) for settling error correction. In the proposed DAC, a non-binary-weighted structure with redundancy is employed for the upper 8-bit capacitor array to reduce the residual voltage settling time requirement, facilitating high-speed operation. The remaining 3-bit capacitor array is composed of three unit capacitors, which are attached to the fractional reference voltages generated from a resistor string (R-string). The proposed partially monotonic switching scheme reduces the switching power consumption and the common-mode voltage variations of the DAC output voltage. The proposed 3D-encapsulated capacitor layout reduces the interference of adjacent signals while securing the high linearity of capacitors. Implemented in a 28 nm CMOS, the proposed ADC consumes 1.67 mW of power with a 1.0 V supply voltage and occupies an active area of 0.026 mm2. The prototype ADC achieves a signal-to-noise-and-distortion-ratio (SNDR) and a spurious-free-dynamic-range (SFDR) of 53.5 dB and 67.5 dB, with a 9 MHz input at 160 MS/s, respectively. |